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Distributed processing with the Z8000 family
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Source AFIPS Joint Computer Conferences archive
Proceedings of the June 7-10, 1982, national computer conference table of contents
Houston, Texas
SESSION: Hardware/computer architecture table of contents
Pages 53-57  
Year of Publication: 1982
ISBN ~ ISSN:0095-6880 , 0-88283-035-X
Authors
Richard Mateosian  Zilog, Campbell, California
Janak Pathak  Zilog, Campbell, California
Sponsor
AFIPS : American Federation of Information Processing Societies
Publisher
ACM  New York, NY, USA
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abstract   collaborative colleagues  

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ABSTRACT

The Z8000 Family plan philosophy envisions a distributed processing approach to many Z8000 applications. The Z8000 Family consists of CPUs, CPU support circuits, and a full complement of VLSI peripherals. These components are all integrated by the Z-BUS, which defines the interconnections and transactions among them. The basic philosophy of the family plan is that of distribution of intelligence and function among complementary VLSI components. Of the several possible realizations of this philosophy, the one chosen has the following major aspects:

1. Synchronization primitives in bus and component architectures

2. Extensively programmable VLSI peripherals and CPU support circuits

3. Bus support for cooperative transactions

4. Built-in support for interprocess message passing

Collaborative Colleagues:
Richard Mateosian: colleagues
Janak Pathak: colleagues