The fault-tolerant 3B-20 processor

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The fault-tolerant 3B-20 processor

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AFIPS Joint Computer Conferences archive
Proceedings of the May 4-7, 1981, national computer conference table of contents

Chicago, Illinois

SESSION: Computer hardware and architecture table of contents

Pages 41-48

Year of Publication: 1981

Authors

L. E. Gallaher	Bell Telephone Laboratories, Naperville, Illinois
W. N. Toy	Bell Telephone Laboratories, Naperville, Illinois

Sponsor

AFIPS : American Federation of Information Processing Societies

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 0

Additional Information:

abstract references collaborative colleagues

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ABSTRACT

The 3B-20 is the first Bell System general-purpose telecommunication processor designed to meet a broad range of applications. New features such as memory management are incorporated into its design to support a modern operating system. Hardware supports are provided to efficiently execute a high-level language. The 3B-20 Processor is designed to meet ESS reliability requirements and the proven technique of self-checking duplex operation forms its basic architecture structure.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	"No. 1 ESS Description," BSTJ, September, 1968.
	2	"No. 2 ESS Description," BSTJ, October, 1969.
	3	No. 1A Processor Description," BSTJ, February, 1977.
	4	B. W. Kernighan , D. M. Ritchie, The C programming language, Prentice-Hall, Inc., Upper Saddle River, NJ, 1978
	5	Toy, W. N. "Fault Tolerant Design of ESS Processors," Proceedings IEEE, October 1978.
	6	Storey, T. F., "Design of a Microprogram Control for a Processor in an Electronic-Switching System." BSTJ, February 1976.
	7	AMD. The Am2900 Family Data Book. 1979.

Collaborative Colleagues:

L. E. Gallaher: colleagues

W. N. Toy: colleagues

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