A study of fault tolerance techniques for associative processors

ABSTRACT

Associative processing techniques have been suggested for numerous application areas and have been proven to be superior to more conventional procedures for a number of specialized applications. Recent advances in computer technology and development of new architectural concepts for associative devices have made the design of larger and more flexible systems possible. Such systems are extremely complex and must be adequately protected against failures. This paper reports on the results of a study which has indicated the techniques that are applicable and difficulties that may be encountered in the design of fault-tolerant associative processors.

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