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Working set restoration: a method to increase the performance of multilevel storage hierarchies
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Source AFIPS Joint Computer Conferences archive
Proceedings of the June 7-10, 1976, national computer conference and exposition table of contents
New York, New York
SESSION: Systems: computer systems table of contents
Pages 373-380  
Year of Publication: 1976
Author
Peter Schneider  Siemens AG, Munich, Germany
Sponsor
AFIPS : American Federation of Information Processing Societies
Publisher
ACM  New York, NY, USA
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ABSTRACT

The emergence of new storage technologies such as Charge Coupled Devices (CCD) and Bubbles with access times which lie in the access gap between semiconductor memories and rotating magnetic storage media is another important step toward implementing multilevel storage hierarchies.

However, a comparison between a three-level storage system, consisting of cache, page buffer and CCD main memory, and a conventional two-level main memory system will show that the three-level hierarchy using the transfer on demand strategy has an effective access time which is higher by about a factor of 2.

Yet, through better use of the program locality the access time of a three-level system can be reduced to that of the two-level cache/page buffer system. Using this method, the so-called working set restoration, the working set of pages of the next program to be run is loaded into the page buffer during execution of the active program. The required page transfer operations are executed concealed and are thus not time-critical for the processor. This means that for program processing only the access time to the two-level system becomes apparent.

The advantage of a three-level system of this type lies not so much in the improved performance but rather in the lower costs, since it permits the use of a large-capacity main memory on a technology level which is cheaper by a factor of 2 to 4 as compared with MOS RAM.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Bhandakar, D. P., "Cost Performance Aspects of CCD Fast Auxiliary Memory," Proc. CCD '75', Charge-Coupled Devices Appl. Conf., 1975, San Diego, pp. 435--442.
 
2
Boyle, W. S., and G. E. Smith, "Charge Coupled Semiconductor Devices," Bell Syst. Tech. J., 49, 1970, pp. 587--593.
 
3
Ablassmeier, U. and E. Döring, CCD---Schaltungen hoher Speicherdichte in Al-Si-Gate Technologie, Siemens Forsch. -und Entwickl.-Ber. 4, 1975, pp. 226--230.
 
4
Schneider, P. and J. Witte, CCD Memories in a Working Memory System, Siemens Forsch.- und Entwickl.-Ber. 4, 1975, pp. 231--237.
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