CPU-utilization and secondary-storage performance: the demand for a new secondary-storage technology

ABSTRACT

Previous studies investigated the usability of charge-coupled devices (CCDs) in the context of economies to be achieved in main memory capacity. In systems with virtual memories, such economies result from the use of fast paging devices. In spite of the concomitant savings in main memory costs, which will probably be eaten up by the costs of the new-technology paging device, the price/performance ratio must be expected to be less favorable than that of conventional systems, since the share of the operating system software required for page fault handling will increase.

More recent research has shown, however, that not only the degree of multiprogramming, i.e., the number of processes required to cover an I/O time interval, is a factor of crucial importance for optimum CPU utilization, but also the number of disk devices available in the secondary-storage system: unless the number of storage devices is large enough to handle, within an I/O time interval, at least as many parallel I/O operations as are needed to ensure that a sufficient number of processes are again ready for busying the CPU, the aim of full utilization of the CPU cannot be achieved---not even through a higher degree of multiprogramming. With disk devices of ever higher recording densities but otherwise nearly constant performance data becoming available, fewer devices than today will be required in the future to store the on-line data file volume. Since fast, favorably priced central processing units are likewise becoming available, it must be expected that the future systems, unlike the systems of today, will for the first time be beset with the problem of input/output bottlenecks arising from an insufficient number of storage devices. Rather than attempting to achieve the required I/O data rate through a sufficient number of devices operating in parallel, use should therefore be made of such devices as CCD storages in secondary-storage hierarchies, which offer themselves as the less costly solution to the problem.

REFERENCES

• 1: Peter J. Denning, The working set model for program behavior, Communications of the ACM, v.11 n.5, p.323-333, May 1968 [doi>10.1145/363095.363141]
• 2: Mattson, R. L., "Evaluation of multilevel Memories", IEEE Trans. Magn., Vol. MAG-7, Dec. 1971, pp. 814--819.
• 3: Robert M. Meade, On memory system design, Proceedings of the November 17-19, 1970, fall joint computer conference, November 17-19, 1970, Houston, Texas [doi>10.1145/1478462.1478468]
• 4: John W. Boyse , David R. Warn, A Straightforward Model for Computer Performance Prediction, ACM Computing Surveys (CSUR), v.7 n.2, p.73-93, June 1975 [doi>10.1145/356648.356649]
• 5: Bhandaker, D. P., "Cost Performance Aspects of CCD Fast Auxiliary Memory", Proc. CCD '75', Charge-Coupled Devices Appl. Conf., 1975, San Diego, pp. 435--442.
• 6: Pohm, A. V., "Cost/Performance Perspectives of Paging with Electronic and Electromechanical Backing Stores", Proc. of the IEEE, Vol. 63, No. 8, Aug. 1975.
• 7: Peter Schneider, Working set restoration: a method to increase the performance of multilevel storage hierarchies, Proceedings of the June 7-10, 1976, national computer conference and exposition, June 07-10, 1976, New York, New York [doi>10.1145/1499799.1499856]