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System considerations in the NS32032 design
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Source AFIPS Joint Computer Conferences archive
Proceedings of the July 9-12, 1984, national computer conference and exposition table of contents
Las Vegas, Nevada
SESSION: Computer hardware and architectures table of contents
Pages 77-81  
Year of Publication: 1984
ISBN ~ ISSN:0095-6880 , 0-88283-043-0
Author
Richard Mateosian  National Semiconductor, Santa Clara, California
Sponsor
AFIPS : American Federation of Information Processing Societies
Publisher
ACM  New York, NY, USA
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ABSTRACT

The key element in the high-performance systems toward which the 32-bit microprocessors are targeted is the memory and its buses. Viewing memory rather than the CPU as the key system element leads to an important rule for CPU designers: don't hog the bus. The NS32032 avoids hogging the bus by increasing the information content of memory transactions, and by keeping key data where it's needed rather than moving it across the bus each time it's used. The information content of transactions is increased through the use of a wide bus and a compact instruction encoding. Key data is kept in registers and in an MMU translation lookaside buffer.