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ABSTRACT
Increased chip temperature has been known to cause severe reliability problems and to significantly increase leakage power. The register file has been previously shown to exhibit the highest temperature compared to all other hardware components in a modern high-end embedded processor, which makes it particularly susceptible to faults and elevated leakage power. We show that this is mostly due to the highly clustered register file accesses where a set of few registers physically placed close to each other are accessed with very high frequency. We propose compile-time temperature-aware register reallocation methodologies for breaking such groups of registers and to uniformly distribute the accesses to the register file. This is achieved with no performance and no hardware overheads. We show that the underlying problem is NP-hard, and subsequently introduce and evaluate two efficient algorithmic heuristics. Our extensive experimental study demonstrates the efficiency of the proposed methodology.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Agrawal, B. and Sherwood, T. 2006. Guiding architectural sram models. In Proceedings of the International Conference on Computer Design (ICCD).
|
| |
2
|
Amrutur, B. and Horowitz, M. 2000. Speed and power scaling of sram's. IEEE J. Solid-State Circ. 35, 2, 175--185.
|
| |
3
|
Atienza, D., Raghavan, P., Ayala, J., Micheli, G. D., Catthoor, F., Verkest, D., and Lopez-Vallejo, M. 2006. Compiler-driven leakage energy reduction in banked register files. Lecture Notes in Computer Science, vol 4148, 107--116.
|
| |
4
|
Babel, L., Kellerer, H., and Kotov, V. 1998. The k-partitioning problem. Math. Meth. Op. Resea. 47, 1, 59--82.
|
| |
5
|
|
| |
6
|
Coffman, E. G. 1976. Computer and Job-Shop Scheduling Theory. John Wiley & Sons Inc.
|
 |
7
|
|
| |
8
|
Fisher, J., Faraboschi, P., and Young, C. 2005. Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools. Morgan Kaufmann.
|
| |
9
|
Gunther, S., Binns, F., Carmean, D., and Hall, J. 2001. Managing the impact of increasing microprocessor power consumption. Intel Techn. J.
|
| |
10
|
M. R. Guthaus , J. S. Ringenberg , D. Ernst , T. M. Austin , T. Mudge , R. B. Brown, MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop, p.3-14, December 02-02, 2001
[doi> 10.1109/WWC.2001.15]
|
 |
11
|
|
| |
12
|
Kandemir, M., Vijaykrishnan, N., Irwin, M., Ye, W., and Demirkiran, I. 2000. Register relabeling: A post compilation technique for energy reduction. In Proceedings of the Workshop on Compilers and Operating Systems for Low Power (COLP).
|
| |
13
|
Ja Chun Ku , Serkan Ozdemir , Gokhan Memik , Yehea Ismail, Thermal Management of On-Chip Caches Through Power Density Minimization, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.283-293, November 12-16, 2005, Barcelona, Spain
[doi> 10.1109/MICRO.2005.36]
|
| |
14
|
Kursun, E., Cher, C., Buyuktosunoglu, A., and Bose, P. 2006. Investigating the effects of task scheduling on thermal behavior. In Proceedings of the Workshop on Temperature-Aware Computer Systems (TACS).
|
| |
15
|
Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
| |
16
|
|
| |
17
|
Mahajan, R. 2002. Thermal management of cpus: A perspective on trends, needs and opportunities. In Proceedings of THERMINIC-8.
|
 |
18
|
Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin , Rita Chen , Debashree Ghosh, Techniques for low energy software, Proceedings of the 1997 international symposium on Low power electronics and design, p.72-75, August 18-20, 1997, Monterey, California, United States
[doi> 10.1145/263272.263286]
|
 |
19
|
|
| |
20
|
|
 |
21
|
|
| |
22
|
Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan, Temperature-Aware Computer Systems: Opportunities and Challenges, IEEE Micro, v.23 n.6, p.52-61, November 2003
[doi> 10.1109/MM.2003.1261387]
|
 |
23
|
|
| |
24
|
Tarjan, D., Thoziyoor, S., and Jouppi, N. 2006. Cacti 4.0: An integrated cache timing, power and area model. Tech. rep., HP Laboratories Palo Alto.
|
 |
25
|
W. Ye , N. Vijaykrishnan , M. Kandemir , M. J. Irwin, The design and use of simplepower: a cycle-accurate energy estimation tool, Proceedings of the 37th conference on Design automation, p.340-345, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337436]
|
| |
26
|
Yeh, L. and Chu, R. 2001. Thermal Management of Microelectronic Equipment. American Society of Mechanical Engineers.
|
| |
27
|
Zhang, Y. 2003. Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects. Tech. rep., CS-2003-05, University of Virginia.
|
|