Evaluation of data-parallel splitting approaches for H.264 decoding

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Evaluation of data-parallel splitting approaches for H.264 decoding

Full text

Pdf (329 KB)

Source

International Conference on Mobile Computing and Multimedia archive
Proceedings of the 6th International Conference on Advances in Mobile Computing and Multimedia table of contents

Linz, Austria

SESSION: MoMM 2008: Multimedia streaming and decoding table of contents

Pages 40-49

Year of Publication: 2008

ISBN:978-1-60558-269-6

Authors

Florian H. Seitner	Vienna University of Technology
Ralf M. Schreier	Vienna University of Technology
Michael Bleyer	Vienna University of Technology
Margrit Gelautz	Vienna University of Technology

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 106, Citation Count: 0

Additional Information:

abstract references index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1497185.1497198 What is a DOI?

ABSTRACT

The high computational demands of the H.264 decoding process pose serious challenges on current processor architectures. A natural way to tackle this problem is the use of multi-core systems. The contribution of this paper lies in a systematic overview and performance evaluation of parallel video decoding approaches. Our study investigates six methods for accomplishing data-parallel splitting in strongly resource-restricted environments inherent to mobile devices. These methods are compared against each other in terms of run-time complexity, core usage, inter-communication and bus transfers. We present benchmark results using different numbers of processor cores. Our results shall aid in finding a splitting strategy that is best suited for the targeted hardware-architecture.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. Bondarev, M. R. Chaudron, and P. H. d. With. Predictable component-based software design of real-time MPEG-4 video applications. In Proc. of the SPIE, Visual Communications and Image Processing, volume 5960, pages 2288--2298, July 2005.
	2	T.-W. Chen, Y.-W. Huang, T.-C. Chen, Y.-H. Chen, C.-Y. Tsai, and L.-G. Chen. Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. In Proc. of the IEEE Int. Symp. on Circuits and Systems, pages 2931--2934, 2005.
	3	Y.-K. Chen, X. Tian, S. Ge, and M. Girkar. Towards efficient multi-level threading of H.264 encoder on Intel hyper-threading architectures. In Proc. of the 18th Int. Parallel and Distributed Processing Symp., volume 1, pages 63--72, 2004.
	4	ITU-T and ISO/IEC. Advanced video coding for generic audiovisual services (ITU Rec. H.264 \| ISO/IEC 14496-10). ITU-T and ISO/IEC, March 2005.
	5	Joint Model Version 12.2. http://iphome.hhi.de/suehring/tml/. 07.01.2008.
	6	C. Meenderinck, A. Azevedo, M. Alvarez, B. Juurlink, and A. Ramirez. Parallel scalability of H.264. In Proc. of the 1st Workshop on Programmability Issues for Multi-Core Computers, January 2008.
	7	T. Moriyoshi and S. Miura. Real-time H.264 encoder with deblocking filter parallelization. In IEEE Int. Conf. on Consumer Electronics, pages 63--64, 2008.
	8	ON DEMAND Microelectronics AG. http://www.odmsemi.com. 07.01.2008.
	9	A. Rodriguez , A. Gonzalez , M. P. Malumbres, Hierarchical Parallelization of an H.264/AVC Video Encoder, Proceedings of the international symposium on Parallel Computing in Electrical Engineering, p.363-368, September 13-17, 2006 [doi>10.1109/PARELEC.2006.42]
	10	K. Schöffmann, M. Fauster, O. Lampl, and L. Böszörményi. An evaluation of parallelization concepts for baseline-profile compliant H.264/AVC decoders. In Euro-Par 2007, Parallel Processing, pages 782--791, 2007.
	11	F. H. Seitner, R. M. Schreier, M. Bleyer, and M. Gelautz. A macroblock-level analysis on the dynamic behaviour of an H.264 decoder. In IEEE Int. Symp. on Consumer Electronics 2007, pages 1--5, Irving, June 2007.
	12	F. H. Seitner, R. M. Schreier, M. Bleyer, and M. Gelautz. A high-level simulator for the H.264/AVC decoding process in multi-core systems. In Proc. of the SPIE, Multimedia on Mobile Devices 2008, volume 6821, pages 5--12, January 2008.
	13	Shuwei Sun , Dong Wang , Shuming Chen, A Highly Efficient Parallel Algorithm for H.264 Encoder Based on Macro-Block Region Partition, Proceedings of the 3rd international conference on High Performance Computing and Communications, September 26-28, 2007, Houston, Texas, USA [doi>10.1007/978-3-540-75444-2_55]
	14	E. B. van der Tol, E. G. Jaspers, and R. H. Gelderblom. Mapping of H.264 decoding on a multiprocessor architecture. In Proc. of the SPIE, volume 5022, pages 707--718, May 2003.
	15	S. H. Wang, W. H. Peng, Y. He, G. Y. Lin, C. Y. Lin, S. C. Chang, C. N. Wang, and P. Chiang. A platform-based MPEG-4 advanced video coding (AVC) decoder with block level pipelining. In Proc. of the 2003 Joint Conf. of the 4th Int. Conf. on Information, Communications and Signal Processing and the 4th Pacific Rim Conf. on Multimedia, volume 1, pages 51--55, Dec 2003.
	16	Z. Zhao and P. Liang. A highly efficient parallel algorithm for H.264 video encoder. In Proc. of the 31st IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, volume 5, pages 489--492, May 2006.