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Feedback-directed barrier optimization in a strongly isolated STM
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Annual Symposium on Principles of Programming Languages archive
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages table of contents
Savannah, GA, USA
SESSION: Medley II table of contents
Pages 213-225  
Year of Publication: 2009
ISBN:978-1-60558-379-2
Also published in ...
Authors
Nathan G. Bronson  Stanford University, Palo Alto, CA, USA
Christos Kozyrakis  Stanford University, Palo Alto, CA, USA
Kunle Olukotun  Stanford University, Palo Alto, CA, USA
Sponsors
ACM: Association for Computing Machinery
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
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ABSTRACT

Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of abstractions that ease parallel programming. Software transactional memory (STM) addresses many of the complications of concurrency by providing a simple and composable model for safe access to shared data structures. Software transactions extend a language with an atomic primitive that declares that the effects of a block of code should not be interleaved with actions executing concurrently on other threads. Adding barriers to shared memory accesses provides atomicity, consistency and isolation.

Strongly isolated STMs preserve the safety properties of transactions for all memory operations in a program, not just those inside an atomic block. Isolation barriers are added to non-transactional loads and stores in such a system to prevent those accesses from observing or corrupting a partially completed transaction. Strong isolation is especially important when integrating transactions into an existing language and memory model. Isolation barriers have a prohibitive performance overhead, however, so most STM proposals have chosen not to provide strong isolation.

In this paper we reduce the costs of strong isolation by customizing isolation barriers for their observed usage. The customized barriers provide accelerated execution by blocking threads whose accesses do not follow the expected pattern. We use hot swap to tighten or loosen the hypothesized pattern, while preserving strong isolation. We introduce a family of optimization hypotheses that balance verification cost against generality.

We demonstrate the feasibility of dynamic barrier optimization by implementing it in a bytecode-rewriting Java STM. Feedback-directed customization reduces the overhead of strong isolation from 505% to 38% across 11 non-transactional benchmarks; persistent feedback data further reduces the overhead to 16%. Dynamic optimization accelerates a multi-threaded transactional benchmark by 31% for weakly-isolated execution and 34% for strongly-isolated execution.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Intel C++ STM Compiler, Prototype Edition. http://software.intel.com.
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E. Bruneton, R. Lenglet, and T. Coupaye. ASM: a code manipulation tool to implement adaptable systems. Adaptable and Extensible Component Systems, 2002.
 
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J. Chung, H. Chafi, C. Cao Minh, A. McDonald, B. D. Carlstrom, C. Kozyrakis, and K. Olukotun. The Common Case Transactional Behavior of Multithreaded Programs. In Proceedings of the 12th International Conference on High-Performance Computer Architecture, February 2006.
 
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D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In DISC'06: Proceedings of the 20th International Symposium on Distributed Computing, March 2006.
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Specification Request (JSR) 133: Java Memory Model and Thread Specification, September 2004.
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Collaborative Colleagues:
Nathan G. Bronson: colleagues
Christos Kozyrakis: colleagues
Kunle Olukotun: colleagues