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Compact architecture for high-throughput regular expression matching on FPGA
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Source Symposium On Architecture For Networking And Communications Systems archive
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems table of contents
San Jose, California
SESSION: Packet classification table of contents
Pages 30-39  
Year of Publication: 2008
ISBN:978-1-60558-346-4
Authors
Yi-Hua E. Yang  University of Southern California
Weirong Jiang  University of Southern California
Viktor K. Prasanna  University of Southern California
Sponsors
SIGARCH: ACM Special Interest Group on Computer Architecture
SIGCOMM: ACM Special Interest Group on Data Communication
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper we present a novel architecture for high-speed and high-capacity regular expression matching (REM) on FPGA. The proposed REM architecture, based on nondeterministic finite automaton (RE-NFA), efficiently constructs regular expression matching engines (REME) of arbitrary regular patterns and character classes in a uniform structure, utilizing both logic slices and block memory (BRAM) available on modern FPGA devices. The resulting circuits take advantage of synthesis and routing optimizations to achieve high operating speed and area efficiency. The uniform structure of our RE-NFA design can be stacked in a simple way to produce multi-character input circuits to scale up throughput further. An n-state m-character input REME takes only O (n X log2 m) time to construct and occupies no more than O (n X m) logic units. The REMEs can be staged and pipelined in large numbers to achieve high parallelism without sacrificing clock frequency.

Using the proposed RE-NFA architecture, we are able to implement 3 copies of two-character input REMEs, each with 760 regular expressions, 18715 states and 371 character classes, onto a single Xilinx Virtex 4 LX-100-12 device. Each copy processes 2 characters per clock cycle at 300 MHz, resulting in a concurrent throughput of 14.4 Gbps for 760 REMEs. Compared with the automatic NFA-to-VHDL REME compilation [13], our approach achieves over 9x throughput efficiency (Gbps*state/LUT). Compared with state-of-the-art REMEs on FPGA, our approach also indicates up to 70% better throughput efficiency.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Bro Intrusion Detection System. http://bro-ids.org/.
 
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SNORT.ORG. http://www.snort.org/.
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Joao Bispo, Ioannis Sourdis, Joao M. P. Cardoso, and Stamatis Vassiliadis, "Regular Expression Matching for Feconfigurable Packet Inspection", FPT '06: Proceedings of the IEEE International Conference on Field Programmable Technology, 2006., Dec. 2006, pp. 119--126.
 
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Norio Yamagaki, Reetinder Sidhu, and Satoshi Kamiya, "High-Speed Regular Expression Matching Engine Using Multi-Character NFA", FPL '08: Proceedings of the International Conference on Field Programmable Logic and Applications, 2008., Aug. 2008, pp. 697--701.
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Collaborative Colleagues:
Yi-Hua E. Yang: colleagues
Weirong Jiang: colleagues
Viktor K. Prasanna: colleagues