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GRAMPS: A programming model for graphics pipelines
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ACM Transactions on Graphics (TOG) archive
Volume 28 ,  Issue 1  (January 2009) table of contents
Article No. 4  
Year of Publication: 2009
ISSN:0730-0301
Authors
Jeremy Sugerman  Stanford University, Stanford, CA
Kayvon Fatahalian  Stanford University, Stanford, CA
Solomon Boulos  Stanford University, Stanford, CA
Kurt Akeley  Microsoft Research, Mountain View, CA
Pat Hanrahan  Stanford University, Stanford, CA
Publisher
ACM  New York, NY, USA
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ABSTRACT

We introduce GRAMPS, a programming model that generalizes concepts from modern real-time graphics pipelines by exposing a model of execution containing both fixed-function and application-programmable processing stages that exchange data via queues. GRAMPS allows the number, type, and connectivity of these processing stages to be defined by software, permitting arbitrary processing pipelines or even processing graphs. Applications achieve high performance using GRAMPS by expressing advanced rendering algorithms as custom pipelines, then using the pipeline as a rendering engine. We describe the design of GRAMPS, then evaluate it by implementing three pipelines, that is, Direct3D, a ray tracer, and a hybridization of the two, and running them on emulations of two different GRAMPS implementations: a traditional GPU-like architecture and a CPU-like multicore architecture. In our tests, our GRAMPS schedulers run our pipelines with 500 to 1500KB of queue usage at their peaks.


REFERENCES

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1
AMD. 2008a. AMD radeon HD 4800 product documentation. http://ati.amd.com/products/radeonhd4800.
 
2
AMD. 2008b. ATI stream computing web site. http://ati.amd.com/technology/streamcomputing/.
3
4
5
6
7
 
8
9
10
 
11
12
13
 
14
Intel. 2008. Intel thread building blocks product documentation. http://www.intel.com/cd/software/products/asmo-na/eng/294797.htm.
 
15
 
16
17
 
18
19
 
20
MIPS Technologies Inc. 2005. MIPS64 architecture. http://mips.com/products/architectures/mips64/.
 
21
NVIDIA. 2007. NVIDIA CUDA programming guide. http://developer.download.nvidia.com/compute/cuda/1_1/NVIDIA_CUDA_Programming_Guide_1.1.pdf.
 
22
 
23
Pham, D., Asano, S., Bolliger, M., Day, M., Hofstee, H., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Masubuchi, Y., et al. 2005. The design and implementation of a first-generation CELL processor. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'05), 184--186.
 
24
 
25
Segal, M. and Akeley, K. 2006. The OpenGL 2.1 specification. http://www.opengl.org/registry/doc/glspec21.20061201.pdf.
26
 
27
Tarditi, D., Puri, S., and Oglesby, J. 2006. Accelerator: Using data parallelism to program GPUs for general-purpose uses. SIGOPS Oper. Syst. Rev. 40, 5, 325--335.
 
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Collaborative Colleagues:
Jeremy Sugerman: colleagues
Kayvon Fatahalian: colleagues
Solomon Boulos: colleagues
Kurt Akeley: colleagues
Pat Hanrahan: colleagues