Register coalescing techniques for heterogeneous register architecture with copy sifting

ABSTRACT

Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers, which are all gathered in the same register file. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers, which are scattered in physically different register files dedicated for each dissimilar purpose and use. In this work, we show that optimistic coalescing is also useful for an embedded processor to better handle such heterogeneity of the register architecture, and developed a modified algorithm for optimal coalescing that helps a register allocator. In the experiment, an existing register allocator was able to achieve up to 13.0% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme.

REFERENCES

• 1: Ahn, M., Lee, J., Jung, S., Yoon, J. W., and Paek, Y. 2007. A code generation approach for Heterogeneous register architectures. In Proceedings of the 11th Annual Workshop on the Interaction between Compilers and Computer Architecture. IEEE, Los Alamitos, CA.
• 2: Guido Araujo , Sharad Malik, Code generation for fixed-point DSPs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.2, p.136-161, April 1998 [doi>10.1145/290833.290837]
• 3: Peter E. Bergner, Spill code minimization techniques for graph coloring register allocators, University of Minnesota, Minneapolis, MN, 1997
• 4: Preston Briggs, Register allocation via graph coloring, Rice University, Houston, TX, 1992
• 5: G. J. Chaitin, Register allocation & spilling via graph coloring, Proceedings of the 1982 SIGPLAN symposium on Compiler construction, p.98-105, June 23-25, 1982, Boston, Massachusetts, United States
• 6: Jean-Marc Daveau , Thomas Thery , Thierry Lepley , Miguel Santana, A retargetable register allocation framework for embedded processors, Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, June 11-13, 2004, Washington, DC, USA
• 7: H. Feuerhahn, A data-flow driven resource allocation in a retargetable microcode compiler, Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, p.105-107, November 28-December 02, 1988, San Diego, California, United States
• 8: Lal George , Andrew W. Appel, Iterated register coalescing, ACM Transactions on Programming Languages and Systems (TOPLAS), v.18 n.3, p.300-324, May 1996 [doi>10.1145/229542.229546]
• 9: David Koes , Seth Copen Goldstein, A Progressive Register Allocator for Irregular Architectures, Proceedings of the international symposium on Code generation and optimization, p.269-280, March 20-23, 2005 [doi>10.1109/CGO.2005.4]
• 10: Timothy Kong , Kent D. Wilken, Precise register allocation for irregular architectures, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.297-307, November 1998, Dallas, Texas, United States
• 11: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 12: Lee, J. K., Chen, S. Y., and Wu, C. J. 2006. Copy propagation optimizations for VLIW DSP processors with distributed register files. In Proceedings of the 19th International Workshop on Languages and Compilers for Parallel Computing (LCPC). Springer, Berlin, Germany.
• 13: Clifford Liem , Trevor May , Pierre Paulin, Register assignment through resource classification for ASIP microcode generation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.397-402, November 06-10, 1994, San Jose, California, United States
• 14: Jinpyo Park , Soo-Mook Moon, Optimistic register coalescing, ACM Transactions on Programming Languages and Systems (TOPLAS), v.26 n.4, p.735-765, July 2004 [doi>10.1145/1011508.1011512]
• 15: Pierre G. Paulin , Clifford Liem , Trevor C. May , Shailesh Sutarwala, DSP design tool requirements for embedded systems: a telecommunications industrial perspective, Journal of VLSI Signal Processing Systems, v.9 n.1-2, p.23-47, Jan. 1995 [doi>10.1007/BF02406469]
• 16: Stallman, R. M. 1994. Using and Porting GNU CC. Free Software Foundation, Cambridge, MA.
• 17: Bernhard Scholz , Erik Eckstein, Register allocation for irregular architectures, Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems, June 19-21, 2002, Berlin, Germany
• 18: Michael D. Smith , Norman Ramsey , Glenn Holloway, A generalized algorithm for graph-coloring register allocation, Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation, June 09-11, 2004, Washington DC, USA
• 19: Zivojnovic, V., Velarde, J. M., and Schlager, C. 1994. DSPstone: A DSP-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing and Technology. IEEE, Los Alamitos, CA.
• 20: V. Zivojnovic , S. Pees , C. Schlager , M. Willems , R. Schoenen , H. Meyr, DSP processor/compiler co-design: a quantitative approach, Proceedings of the 9th international symposium on System synthesis, p.108, November 06-08, 1996

INDEX TERMS

Primary Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Code generation

Additional Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Optimization; Compilers

General Terms:
Algorithms, Design, Experimentation, Performance

Keywords:
Register allocation, compiler, embedded processors, heterogeneous register architecture, register coalescing