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Design intent coverage revisited
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ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 14 ,  Issue 1  (January 2009) table of contents
Article No. 9  
Year of Publication: 2009
ISSN:1084-4309
Authors
Arnab Sinha  Indian Institute of Technology, Kharagpur, India
Pallab Dasgupta  Indian Institute of Technology, Kharagpur, India
Bhaskar Pal  Indian Institute of Technology, Kharagpur, India
Sayantan Das  Indian Institute of Technology, Kharagpur, India
Prasenjit Basu  Indian Institute of Technology, Kharagpur, India
P. P. Chakrabarti  Indian Institute of Technology, Kharagpur, India
Publisher
ACM  New York, NY, USA
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ABSTRACT

Design intent coverage is a formal methodology for analyzing the gap between a formal architectural specification of a design and the formal functional specifications of the component RTL blocks of the design. In this article we extend the design intent coverage methodology to hybrid specifications containing both state-machines and formal properties. We demonstrate the benefits of this extension in two domains of considerable recent interest, namely (a) the use of auxiliary state-machines in formal specifications, and (b) the use of modest sized RTL blocks in the design intent coverage analysis.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Basu, P., Das, S., Banerjee, A., P. Dasgupta, P. P. C., Mohan, C., Fix, L., and Armoni, R. 2006. Design intent coverage—a new paradigm for formal property verification. Comput.-Aid. Des. Int. Circ. Syst. 25, 10, 1922--1934.
 
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Chockler, H., Kupferman, O., and Vardi, Y. M. 2003. Coverage metrics for formal verification. In Proceedings of the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods. Lecture Notes in Computer Science, vol. 2860, Springer, 111--125.
 
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Pnueli, A. 1977. The complexity of propositional linear temporal logics. In Proceedings of the Foundations of Computer Science. 46--57.
 
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PSL. Property Specification Language (PSL). www.eda.org/vfv/docs/PSL-v1.1.pdf. PSL.
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SVA. SystemVerilog 3.1a Language Reference Manual. www.eda.org/sv/SystemVerilog_3.1a.pdf. SVA.

Collaborative Colleagues:
Arnab Sinha: colleagues
Pallab Dasgupta: colleagues
Bhaskar Pal: colleagues
Sayantan Das: colleagues
Prasenjit Basu: colleagues
P. P. Chakrabarti: colleagues