SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications

ABSTRACT

With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C++/SystemC-based input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SystemCoDesigner, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SystemCoDesigner automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SystemCoDesigner permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SystemCoDesigner is the first fully automated ESL synthesis tool providing a correct-by-construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA.

REFERENCES

• 1: Felice Balarin , Yosinori Watanabe , Harry Hsieh , Luciano Lavagno , Claudio Passerone , Alberto Sangiovanni-Vincentelli, Metropolis: An Integrated Electronic System Design Environment, Computer, v.36 n.4, p.45-52, April 2003 [doi>10.1109/MC.2003.1193228]
• 2: Bluespec, Inc. http://www.bluespec.com.
• 3: Center for Embedded Computer Systems. http://www.cecs.uci.edu/.
• 4: Chantrapornchai, C., Sha, E. H.-M., and Hu, X. S. 2000. Efficient design exploration based on module utility selection. IEEE Trans. CAD Integ. Circ. Sys. 19, 1, 19--29.
• 5: CriticalBlue. http://www.criticalblue.com.
• 6: Falk, J., Haubelt, C., and Teich, J. 2006. Efficient representation and simulation of model-based designs in SystemC. In Proceedings of the Forum on Design Languages. Darmstadt, Germany.
• 7: Forte Design Systems. http://www.forteds.com.
• 8: Thorsten Grotker, System Design with SystemC, Kluwer Academic Publishers, Norwell, MA, 2002
• 9: T. Vinod Kumar Gupta , Purvesh Sharma , M Balakrishnan , Sharad Malik, Processor Evaluation in an Embedded Systems Design Environment, Proceedings of the 13th International Conference on VLSI Design, p.98, January 04-07, 2000
• 10: Soonhoi Ha , Choonseung Lee , Youngmin Yi , Seongnam Kwon , Young-Pyo Joo, Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE, Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, p.207-214, August 16-18, 2006 [doi>10.1109/RTCSA.2006.36]
• 11: Christian Haubelt , Joachim Falk , Joachim Keinert , Thomas Schlichter , Martin Streubühr , Andreas Deyhle , Andreas Hadert , Jürgen Teich, A SystemC-based design methodology for digital signal processing systems, EURASIP Journal on Embedded Systems, v.2007 n.1, p.15-15, January 2007 [doi>10.1155/2007/47580]
• 12: Haubelt, C., Schlichter, T., and Teich, J. 2006. Improving automatic design space exploration by integrating symbolic techniques into multi-objective evolutionary algorithms. Int. J. Comput. Intell. Res. 2, 3, 239--254.
• 13: ITU. 1992. Digital Compression and Coding of Continuous-Tone Still Images—Requirements and Guidelines, T.81 ed. CCITT.
• 14: Tero Kangas , Petri Kukkala , Heikki Orsila , Erno Salminen , Marko Hännikäinen , Timo D. Hämäläinen , Jouni Riihimäki , Kimmo Kuusilinna, UML-based multiprocessor SoC design framework, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.2, p.281-320, May 2006 [doi>10.1145/1151074.1151077]
• 15: Minyoung Kim , Sudarshan Banerjee , Nikil Dutt , Nalini Venkatasubramanian, Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea [doi>10.1145/1176254.1176261]
• 16: Edward A. Lee , Stephen Neuendorffer, Actor-oriented models for codesign: balancing re-use and performance, Formal methods and models for system design: a system level perspective, Kluwer Academic Publishers, Norwell, MA, 2004
• 17: Lee, E. A., Neuendorffer, S., and Wirthlin, M. J. 2003. Actor-oriented design of embedded hardware and software systems. J. Circ. Syst. Comput. 12, 3, 231--260.
• 18: Rainer Leupers, Code Optimization Techniques for Embedded Processors: Methods, Algorithms, and Tools, Kluwer Academic Publishers, Norwell, MA, 2000
• 19: Stylianos Mamagkakis , David Atienza , Christophe Poucet , Francky Catthoor , Dimitrios Soudris , Jose M. Mendias, Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
• 20: Mentor Graphics Corp. http://www.mentor.com.
• 21: S. Mohanty , V. K. Prasanna , S. Neema , J. Davis, Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation, Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems, June 19-21, 2002, Berlin, Germany
• 22: Praveen K. Murthy , Shuvra S. Bhattacharyya, Memory Management for Synthesis of DSP Software, CRC Press, Inc., Boca Raton, FL, 2006
• 23: NEC System Technologies, Ltd. http://www.cyberworkbench.com.
• 24: Hristo Nikolov , Todor Stefanov , Ed Deprettere, Multi-processor system design with ESPAM, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea [doi>10.1145/1176254.1176306]
• 25: Patel, H. D., Shukla, S. K., Mednick, E., and Nikhil, R. S. 2006. A rule-based model of computation for SystemC: integrating SystemC and bluespec for co-design. In Proceedings of International Conference on Formal Methods and Models for Co-Design. 39--48.
• 26: Andy D. Pimentel , Cagkan Erbas , Simon Polstra, A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels, IEEE Transactions on Computers, v.55 n.2, p.99-112, February 2006 [doi>10.1109/TC.2006.16]
• 27: PPM format specification. http://netpbm.sourceforge.net/doc/ppm.html.
• 28: Daniel L. Rosenband , Arvind, Modular scheduling of guarded atomic actions, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996583]
• 29: Thomas Schlichter , Martin Lukasiewycz , Christian Haubelt , Jurgen Teich, Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms, Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, p.309, March 02-03, 2006 [doi>10.1109/ISVLSI.2006.57]
• 30: Todor Stefanov , Claudiu Zissulescu , Alexandru Turjan , Bart Kienhuis , Ed Deprettere, System Design Using Kahn Process Networks: The Compaan/Laura Approach, Proceedings of the conference on Design, automation and test in Europe, p.10340, February 16-20, 2004
• 31: Karsten Strehl , Lothar Thiele , Matthias Gries , Dirk Ziegenbein , Rolf Ernst , Jürgen Teich, FunState—an internal design representation for codesign, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.4, p.524-544, Aug. 2001 [doi>10.1109/92.931229]
• 32: M. Streubühr , J. Falk , Ch. Haubelt , J. Teich , R. Dorsch , Th. Schlipf, Task-accurate performance modeling in SystemC for real-time multi-processor architectures, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
• 33: Synplicity. http://www.synplicity.com.
• 34: XILINX 2005. Embedded SystemTools Reference Manual—Embedded Development Kit EDK 8.1i. XILINX.
• 35: Zitzler, E., Laumanns, M., and Thiele, L. 2002. SPEA2: Improving the strength pareto evolutionary algorithm for multiobjective optimization. In Proceedings of the Conference on Evolutionary Methods for Design, Optimisation, and Control. 19--26.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Experimentation, Languages

Keywords:
System design, hardware/software codesign