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The PARSEC benchmark suite: characterization and architectural implications
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Proceedings of the 17th international conference on Parallel architectures and compilation techniques table of contents
Toronto, Ontario, Canada
SESSION: Analyzing applications table of contents
Pages 72-81  
Year of Publication: 2008
ISBN:978-1-60558-282-5
Authors
Christian Bienia  Princeton University, Princeton, NJ, USA
Sanjeev Kumar  Intel, Santa Clara, CA, USA
Jaswinder Pal Singh  Princeton University, Princeton, NJ, USA
Kai Li  Princeton University, Princeton, NJ, USA
Sponsors
ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Previous available benchmarks for multiprocessors have focused on high-performance computing applications and used a limited number of synchronization methods. PARSEC includes emerging applications in recognition, mining and synthesis (RMS) as well as systems applications which mimic large-scale multithreaded commercial programs. Our characterization shows that the benchmark suite covers a wide spectrum of working sets, locality, data sharing, synchronization and off-chip traffic. The benchmark suite has been made available to the public.


REFERENCES

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CITED BY  13

Collaborative Colleagues:
Christian Bienia: colleagues
Sanjeev Kumar: colleagues
Jaswinder Pal Singh: colleagues
Kai Li: colleagues