ACM Home Page
Please provide us with feedback. Feedback
Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults
Full text PdfPdf (503 KB)
Source
PACT archive
Proceedings of the 17th international conference on Parallel architectures and compilation techniques table of contents
Toronto, Ontario, Canada
SESSION: CMP architecture design table of contents
Pages 43-51  
Year of Publication: 2008
ISBN:978-1-60558-282-5
Authors
Bogdan F. Romanescu  Duke University, Durham, NC, USA
Daniel J. Sorin  Duke University, Durham, NC, USA
Sponsors
ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 12,   Downloads (12 Months): 119,   Citation Count: 3
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1454115.1454124
What is a DOI?

ABSTRACT

To improve the lifetime performance of a multicore chip with simple cores, we propose the Core Cannibalization Architecture (CCA). A chip with CCA provisions a fraction of the cores as cannibalizable cores (CCs). In the absence of hard faults, the CCs function just like normal cores. In the presence of hard faults, the CCs can be cannibalized for spare parts at the granularity of pipeline stages. We have designed and laid out CCA chips composed of multiple OpenRISC 1200 cores. Our results show that CCA improves the chips' lifetime performances, compared to chips without CCA.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
 
3
 
4
L. Carter, J. Feo, and A. Snavely. Performance and Programming Experience on the Tera MTA. In Proceedings of the SIAM Conference on Parallel Processing, Mar. 1999.
 
5
Cisco Systems. Cisco Carrier Router System. http://www.cisco.com/application/pdf/en/us/guest/products/ps5763/c1031/cdcco% nt_0900aecd800f8118.pdf, Oct. 2006.
6
 
7
 
8
R. Ho, K. W. Mai, and M. A. Horowitz. The Future of Wires. Proceedings of the IEEE, 89(4):490--504, Apr. 2001.
9
10
 
11
 
12
D. Lampret. OpenRISC 1200 IP Core Specification, Rev. 0.7. http://www.opencores.org, Sept. 2001.
 
13
 
14
T. Nakura, K. Nose, and M. Mizuno. Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. In Proceedings of IEEE International Solid-State Circuits Conference, 2007.
15
 
16
M. Shah et al. UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC. In Proceedings of the IEEE Asian Solid-State Circuits Conference, pages 22--25, Nov. 2007.
 
17
18
 
19
L. Spainhower and T. A. Gregg. IBM S/390 Parallel Enterprise Server G5 Fault Tolerance: A Historical Perspective. IBM Journal of Research and Development, 43(5/6), September/November 1999.
20
 
21
22
 
23
Y. Sugure et al. Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. IEICE Transactions on Electronics, E89-C(6), June 2006.
 
24
 
25


Collaborative Colleagues:
Bogdan F. Romanescu: colleagues
Daniel J. Sorin: colleagues