| Slack analysis in the system design loop |
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International Conference on Hardware Software Codesign
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Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
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Atlanta, GA, USA
SESSION: System level design: throughput, dependability, coherence, and yield
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Pages 231-236
Year of Publication: 2008
ISBN:978-1-60558-470-6
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Downloads (6 Weeks): 4, Downloads (12 Months): 52, Citation Count: 0
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ABSTRACT
We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by substituting, in the design the loop, the time-consuming simulation step with a fast timing update routine. As a result, we can significantly reduce the design time from on the order of hours/days to the order of seconds/minutes. The update algorithm is defined on the Transaction Level Model (TLM) and can be used by any design flow that invokes TLM-based optimizations. This algorithm has linear-time complexity in the program size and experimental results indicate that any loss of accuracy due to this technique is negligible (< ±1%); the benefit is a reduction in total design cycle time from several hours to a matter of seconds.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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