Asynchronous transient resilient links for NoC

ABSTRACT

This paper proposes a new link for asynchronous NoC communications that is resilient to transient faults on the wires of the link without impact on the data transfer capability. Resilience to transients is achieved by exploiting the phase relationship between data symbols and a common reference symbol where the symbols are transmitted using additional wires. Detection of transient faults is performed by comparison of the data symbol and the reference symbol. We demonstrate it is possible to achieve a similar number of transitions per bit as existing delay insensitive codes, from a power consumption point of view, but achieving resilience to transient faults. The link has been synthesized and validated using 0.12 ¼m technology and power, area and performance are given. It has been shown that the link area cost is 409 ¼m² per data bit and energy per bit is 356 fJ/bit. Latency through the link is 0.8 ns and the maximum operating frequency or throughput of the link is 1.056 GHz.

REFERENCES

• 1: M. Amde, et al "Asynchronous on-chip networks," in Systemon-Chip: Next Generation Electronics, B. M. Al-Hashimi, Ed.: IEE, 2006, pp. 625--52.
• 2: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 3: William J. Dally , Brian Towles, Route packets, not wires: on-chip inteconnection networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 4: S. Ogg , E. Valli , B. Al-Hashimi , A. Yakovlev , C. D'Alessandro , L. Benini, Serialized asynchronous links for NoC, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany [doi>10.1145/1403375.1403617]
• 5: W. J. Bainbridge , S. B. Furber, Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding, Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems, p.118, March 11-14, 2001
• 6: Crescenzo D'Alessandro , Delong Shang , Alex Bystrov , Alex Yakovlev , Oleg Maevsky, Multiple-Rail Phase-Encoding for NoC, Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems, p.107, March 13-15, 2006 [doi>10.1109/ASYNC.2006.23]
• 7: Mark E. Dean , Ted E. Williams , David L. Dill, Efficient self-timing with level-encoded 2-phase dual-rail (LEDR), Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.55-70, April 1991
• 8: T. Verhoeff, "Delay-insensitive codes -- an overview " Distributed Computing, vol. 3, Number 1, 1998.
• 9: Peggy B. McGee , Melinda Y. Agyekum , Moustafa A. Mohamed , Steven M. Nowick, A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication, Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems, p.116-127, April 07-10, 2008 [doi>10.1109/ASYNC.2008.24]
• 10: Eric Dupont , Michael Nicolaidis , Peter Rohr, Embedded Robustness IPs for Transient-Error-Free ICs, IEEE Design & Test, v.19 n.3, p.56-70, May 2002
• 11: Teijo Lehtonen et al "Online Reconfigurable Self-Timed Links for Fault Tolerant NoC," VLSI Design, 2007.
• 12: Arthur Pereira, et al "Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk," ITC '06, pp. 1--9.
• 13: Daniele Rossi , Paolo Angelini , Cecilia Metra, Configurable Error Control Scheme for NoC Signal Integrity, Proceedings of the 13th IEEE International On-Line Testing Symposium, p.43-48, July 08-11, 2007 [doi>10.1109/IOLTS.2007.24]
• 14: H. Po-Tsang, et al "Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip," in NoCS 2008.
• 15: Alireza Ejlali , Bashir M. Al-Hashimi, SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), p.67-76, April 07-10, 2008
• 16: R. Dobkin et al., "Fast Asynchronous Bit-Serial Interconnects for Network-On-Chip," in CCIT TR529 Technion: EE dept, 2005.
• 17: ST-Microelectronics, CORE9GPHS HCMOS9 TEC 3.2.a vol. UNICAD2.4 / December 14, 2001, 2001.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Asynchronous/synchronous operation

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Reliability

Keywords:
asynchronous, network-on-chip, point to point link, reliability, transient faults