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Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs
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International Conference on Hardware Software Codesign archive
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis table of contents
Atlanta, GA, USA
SESSION: Simulation and verification of embedded systems table of contents
Pages 125-130  
Year of Publication: 2008
ISBN:978-1-60558-470-6
Authors
J. P. Grossman  D. E. Shaw Research, New York, NY, USA
Cliff Young  D. E. Shaw Research, New York, NY, USA
Joseph A. Bank  D. E. Shaw Research and Reservoir Labs, New York, NY, USA
Kenneth Mackenzie  D. E. Shaw Research and Reservoir Labs, New York, NY, USA
Douglas J. Ierardi  D. E. Shaw Research, New York, NY, USA
John K. Salmon  D. E. Shaw Research, New York, NY, USA
Ron O. Dror  D. E. Shaw Research, New York, NY, USA
David E. Shaw  D. E. Shaw Research, New York, NY, USA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
SIGBED: ACM Special Interest Group on Embedded Systems
ACM: Association for Computing Machinery
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

Anton, a special-purpose parallel machine currently under construction, is the result of a significant hardware-software codesign effort that relied heavily on an architectural simulator. One of this simulator's many important roles is to support the development of embedded software (software that runs on Anton's ASICs), which is challenging for several reasons. First, the Anton ASIC is a heterogeneous multicore system-on-a-chip, with three types of embedded cores tightly coupled to special-purpose hardware units. Second, a standard 512-ASIC configuration contains a total of 6,656 distinct embedded cores, all of which must be explicitly modeled within the simulator. Third, a portion of the embedded software is dynamically generated at simulation time.

This paper discusses the various ways in which the Anton simulator addresses these challenges. We use a hardware abstraction layer that allows embedded software source code to be compiled without modification for either the simulation host or the hardware target. We report on the effectiveness of embedding golden-model testbenches within the simulator to verify embedded software as it runs. We also describe our hardware-software cosimulation strategy for dynamically generated embedded software. Finally, we use a methodology that we refer to as concurrent mixed-level simulation to model embedded cores within massively parallel systems. These techniques allow the Anton simulator to serve as an efficient platform for embedded software development.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
J. P. Grossman: colleagues
Cliff Young: colleagues
Joseph A. Bank: colleagues
Kenneth Mackenzie: colleagues
Douglas J. Ierardi: colleagues
John K. Salmon: colleagues
Ron O. Dror: colleagues
David E. Shaw: colleagues