| A performance-oriented hardware/software partitioning for datapath applications |
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International Conference on Hardware Software Codesign
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Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
table of contents
Atlanta, GA, USA
SESSION: Performance enhancement-new techniques for FPGAs and partitioning
table of contents
Pages 55-60
Year of Publication: 2008
ISBN:978-1-60558-470-6
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Downloads (6 Weeks): 8, Downloads (12 Months): 78, Citation Count: 0
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ABSTRACT
This article proposes a hardware/software partitioning method targeted to performance-constrained systems for datapath applications. Exploiting a platform based design, a Timed Petri Net formalism is proposed to represent the mapping of the application onto the platform, allowing to statically extract performance estimations in early phases of the design process and without the need of expensive simulations. The mapping process is generalized in order to allow an automatic exploration of the solution space, that identifies the best performance/area configurations among several application-architecture combinations. The method is evaluated implementing a typical datapath performance constrained system, i.e. a packet processing application.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Christian Haubelt , Joachim Falk , Joachim Keinert , Thomas Schlichter , Martin Streubühr , Andreas Deyhle , Andreas Hadert , Jürgen Teich, A SystemC-based design methodology for digital signal processing systems, EURASIP Journal on Embedded Systems, v.2007 n.1, p.15-15, January 2007
[doi> 10.1155/2007/47580]
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W. M. Zubereck, Timed Petri Nets - definitions, properties and applications; Microelectronic and Reliability, pp 627--644, 1991.
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P. Maciel, E. Barros, W. Rosenstiel, A Petri Net Model for Hardware/Software Codesign, Journal Design Automation for Embedded Systems, Springer, 1999.
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T. Murata, Petri Nets: Properties, Analysis and Applications, Proceedings IEEE, Vol.77, N.4, 1989.
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RFC1812: Requirements for IP Version 4 Routers, RFC Editor, United States, 1995.
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Altera Corporation website, www.altera.com.
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CPN Tools website, www.daimi.au.dk/CPnets/.
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