| A time-predictable system initialization design for huge-capacity flash-memory storage systems |
| Full text |
Pdf
(151 KB)
|
Source
|
International Conference on Hardware Software Codesign
archive
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
table of contents
Atlanta, GA, USA
SESSION: Flash memory management
table of contents
Pages 13-18
Year of Publication: 2008
ISBN:978-1-60558-470-6
|
|
Author
|
|
Chin-Hsien Wu
|
National Taiwan University of Science and Technology, Taipei, Taiwan Roc
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 13, Downloads (12 Months): 152, Citation Count: 0
|
|
|
ABSTRACT
The capacity of flash-memory storage systems grows at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges in system designs. How to provide an expected system initialization time for huge-capacity flash-memory storage systems has become an important research topic. In this paper, a time-predictable system initialization design is proposed for huge-capacity flash-memory storage systems. The objective of the design is to provide an expected system initialization time based on a coarse-grained flash translation layer. The time-predictable analysis of the design is provided to discuss the relation between the size of main memory and the system initialization time. The system initialization time can be also estimated and predicted by the time-predictable analysis.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, "A Space-Efficient Flash Translation Layer for Compact-Flash Systems,"IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, MAY 2002.
|
| |
3
|
U.S. Pat. No. 5,937,425 "FLASH FILE SYSTEM OPTIMIZED FOR PAGE-MODE FLASH TECHNOLOGIES"
|
| |
4
|
R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to Flash Memory," Proceedings of The IEEE, Vol. 91, No. 4, April 2003.
|
| |
5
|
Samsung Electronics. NAND flash-memory datasheet and SmartMedia databook, 2006.
|
 |
6
|
|
 |
7
|
|
| |
8
|
Soo-Young Kim and Sung-In Jung, "A Log-based Flash Translation Layer for Large NAND Flash Memory," ICACT, Feb 2006.
|
| |
9
|
Sang-Won Lee, Won-Kyoung Choi, and Dong-Joo Park, "FAST: An Efficient Flash Trnaslation Layer for Flash Memory," EUC Workshop 2006.
|
| |
10
|
Chanik Park , Wonmoon Cheon , Yangsup Lee , Myoung-Soo Jung , Wonhee Cho , Hanbin Yoon, A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications, Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping, p.202-208, May 28-30, 2007
[doi> 10.1109/RSP.2007.8]
|
 |
11
|
|
| |
12
|
D. Woodhouse, Red Hat, Inc. "JFFS: The Journalling Flash File System".
|
| |
13
|
Intel Corporation, "LFS File Manager Software: LFM".
|
| |
14
|
Aleph One Company, "Yet Another Flash Filing System".
|
 |
15
|
|
| |
16
|
Intel Corporation, "Understanding the Flash Translation Layer(FTL)Specification".
|
| |
17
|
Intel Corporation, "Software Concerns of Implementing a Resident Flash Disk".
|
| |
18
|
Intel Corporation, "FTL Logger Exchanging Data with FTL Systems".
|
|