Active control and digital rights management of integrated circuit IP cores

ABSTRACT

We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotely monitor, control, enable, or disable each individual IP on each chip. The approach introduces a paradigm shift in the microelectronic business model, nurturing smaller businesses, and supporting the design-reuse paradigm. The IPs can be controlled by the original designer or by the designers who reuse them. Each IP has a built-in functional lock that pertains to the unique unclonable ID of the chip. A control structure that coordinates the locking and unlocking of the IPs is embedded within the IC. We introduce a trusted third party approach for issuing certificates of authenticity, in case it is required for the applications. We present methods for safeguarding the approach against two attack sources: the foundry (fab), and the reuser. Experimental results show that our approach can be implemented with low area, power, and delay overheads making it suitable for embedded systems. The introduced control method is also low overhead in terms of the added steps to the current design and manufacturing flow.

REFERENCES

• 1: "Certicom application note: Certicom security for fabless semiconductor design companies". http://www.certicom.com/download/aid603/appnotes-fabless.pdf.
• 2: "Design and reuse website", http://www.us.design-reuse.com/.
• 3: "The international technology roadmap for semiconductors (itrs)", http://www.itrs.net/.
• 4: "Defense science board (DSB) study on high performance microchip supply". http://www.acq.osd.mil/dsb/reports/2005-02-hpms report_final.pdf, 2005.
• 5: Yousra M. Alkabani , Farinaz Koushanfar, Active hardware metering for intellectual property protection and security, Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium, p.1-16, August 06-10, 2007, Boston, MA
• 6: Y. Alkabani, F. Koushanfar, N. Kiyavash, and M. Potkonjak. Trusted integrated circuits: A nondestructive hidden characteristics extraction approach. In Information Hiding (IH), 2008.
• 7: Yousra Alkabani , Farinaz Koushanfar , Miodrag Potkonjak, Remote activation of ICs for piracy prevention and digital right management, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
• 8: Yousra Alkabani , Tammara Massey , Farinaz Koushanfar , Miodrag Potkonjak, Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California [doi>10.1145/1391469.1391624]
• 9: Ross J. Anderson, Security Engineering: A Guide to Building Dependable Distributed Systems, John Wiley & Sons, Inc., New York, NY, 2001
• 10: Blaise Gassend , Dwaine Clarke , Marten van Dijk , Srinivas Devadas, Silicon physical random functions, Proceedings of the 9th ACM conference on Computer and communications security, November 18-22, 2002, Washington, DC, USA [doi>10.1145/586110.586132]
• 11: Blaise Gassend , Dwaine Clarke , Marten van Dijk , Srinivas Devadas, Delay-based circuit authentication and applications, Proceedings of the 2003 ACM symposium on Applied computing, March 09-12, 2003, Melbourne, Florida [doi>10.1145/952532.952593]
• 12: Jorge Guajardo , Sandeep S. Kumar , Geert-Jan Schrijen , Pim Tuyls, FPGA Intrinsic PUFs and Their Use for IP Protection, Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems, September 10-13, 2007, Vienna, Austria [doi>10.1007/978-3-540-74735-2_5]
• 13: John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
• 14: Margarida F. Jacome , Helvio P. Peixoto, A Survey of Digital Design Reuse, IEEE Design & Test, v.18 n.3, p.98-107, May 2001 [doi>10.1109/54.922806]
• 15: J. Lee, L. Daihyun, B. Gassend, G. Suh, M. van Dijk, and S. Devadas. A technique to build a secret key in integrated circuits for identification and authentication applications. In Symposium of VLSI Circuits, pages 176--179, 2004.
• 16: K. Lofstrom, W. Daasch, and D. Taylor. IC identification circuits using device mismatch. In International Solid State Circuits Conference (ISSCC), pages 372--373, 2000.
• 17: M. Majzoobi, F. Koushanfar, and M. Potkonjak. Lightweight secure PUF. In International conference on computer-aided design (ICCAD), 2008.
• 18: M. Majzoobi, F. Koushanfar, and M. Potkonjak. Testing techniques for hardware security. In ITC, 2008.
• 19: C. Marsh and T. Kean. A security tagging scheme for asic designs and intellectual property cores. Design & Reuse, January 2007.
• 20: A. Oliveira. Techniques for the creation of digital watermarks in sequential circuit designs. IEEE Trans. CAD of Integrated Circuits and Systems, 20(9):1101--1117, 2001.
• 21: G. Qu and M. Potkonjak. Intellectual Property Protection in VLSI Design. Kluwer Academic Publisher, 2003.
• 22: James A. Rowson , Alberto Sangiovanni-Vincentelli, Interface-based design, Proceedings of the 34th annual conference on Design automation, p.178-183, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266060]
• 23: Jarrod A. Roy , Farinaz Koushanfar , Igor L. Markov, EPIC: ending piracy of integrated circuits, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany [doi>10.1145/1403375.1403631]
• 24: Steve Trimberger, Trusted design in FPGAs, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278483]
• 25: Thomas Wollinger , Jorge Guajardo , Christof Paar, Security on FPGAs: State-of-the-art implementations and attacks, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.3, p.534-574, August 2004 [doi>10.1145/1015047.1015052]
• 26: L. Yuan and G. Qu. Information hiding in finite state machine. In Information Hiding Workshop, pages 340--354, 2004.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.m Miscellaneous

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.m Miscellaneous

  K. Computing Milieux
  K.6 MANAGEMENT OF COMPUTING AND INFORMATION SYSTEMS
      K.6.5 Security and Protection (D.4.6, K.4.2)

General Terms:
Design, Management, Security

Keywords:
IP protection, active IP control, security