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Reducing pressure in bounded DBT code caches
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International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems table of contents
Atlanta, GA, USA
SESSION: Caching and its impact table of contents
Pages 109-118  
Year of Publication: 2008
ISBN:978-1-60558-469-0
Authors
José A. Baiocchi  University of Pittsburgh, Pittsburgh, PA, USA
Bruce R. Childers  University of Pittsburgh, Pittsburgh, PA, USA
Jack W. Davidson  University of Virginia, Charlottesville, VA, USA
Jason D. Hiser  University of Virginia, Charlottesville, VA, USA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight constraints on memory and performance. A DBT uses a software-managed code cache to hold blocks of translated code. To minimize overhead, the code cache is usually large so blocks are translated once and never discarded. However, an embedded system may lack the resources for a large code cache. This constraint leads to significant slowdowns due to the retranslation of blocks prematurely discarded from a small code cache. This paper addresses the problem and shows how to impose a tight size bound on the code cache without performance loss. We show that about 70% of the code cache is consumed by instructions that the DBT introduces for its own purposes. Based on this observation, we propose novel techniques that reduce the amount of space required by DBT-injected code, leaving more room for actual application code and improving the miss ratio. We experimentally demonstrate that a bounded code cache can have performance on-par with an unbounded one.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. Guha, K. Hazelwood, and M. L. Soffa. Reducing exit stub memory consumption in code caches. In Int'l. Conf. on High Performance Embedded Architectures and Compilers (HiPEAC), 2007.
 
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Intel Corporation. Intel PXA27x Processor Family Developer's Manual, 2006.
 
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Collaborative Colleagues:
José A. Baiocchi: colleagues
Bruce R. Childers: colleagues
Jack W. Davidson: colleagues
Jason D. Hiser: colleagues