ACM Home Page
Please provide us with feedback. Feedback
Digital Library logoTake a look at the new version of this page: [ beta version ]. Tell us what you think.
Design and implementation of a framework for creating portable and efficient packet-processing applications
Full text PdfPdf (304 KB)
Source
International Conference On Embedded Software archive
Proceedings of the 8th ACM international conference on Embedded software table of contents
Atlanta, GA, USA
SESSION: Virtual machines, compilers, memory management table of contents
Pages: 237-244  
Year of Publication: 2008
ISBN:978-1-60558-468-3
Authors
Olivier Morandi  Politecnico di Torino, Torino, Italy
Fulvio Risso  Politecnico di Torino, Torino, Italy
Silvio Valenti  TELECOM-ParisTech, Paris, France
Paolo Veglia  TELECOM-ParisTech, Paris, France
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 95,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1450058.1450091
What is a DOI?

ABSTRACT

It is a common belief that using a virtual machine for portable executions of data-plane packet-processing applications would introduce too many penalties in terms of performance, because of the assumed overhead caused by the presence of a hardware abstraction layer. Even if common sense proves true in the case of general purpose virtual machines, such as the JVM and the CLR, it may be wrong in case of a special-purpose network-oriented virtual machine. This paper describes the architecture of a run-time environment and a compiler infrastructure for the Network Virtual Machine (NetVM), showing that the portability of packet-processing programs can be achieved without additional penalties even over heterogeneous platforms. Our implementation supports three different target architectures: one with a general purpose processor (Intel x86), one with a multi-core network processor (Cavium Octeon) and one with a systolic-array network processor (Xelerated X11), and shows that the NetVM model (i) is able to abstract such heterogeneous platforms and (ii) enables the exploitation of hardware functionalities provided by the specific architecture; finally, it demonstrates that the performances of NetVM programs compiled into native code are comparable to those obtained using commercial general purpose compilers.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Baldi and F. Risso. Towards effective portability of packet handling applications across heterogeneous hardware platforms. In IWAN 2005: Proceedings of the 7th Annual International Working Conference on Active and Programmable Networks, Sophia Antipolis, France, November 2005.
 
2
M. Baldi and F. Risso. A framework for rapid development and portable execution of packet-handling applications. In ISSPIT 2005: Proceedings of the 5th IEEE International Symposium on Signal Processing and Information Technology, Athens, Greece, December 2005.
 
3
Cavium. Networks. Octeon Network Processors. http://www.caviumnetworks.com
 
4
Xelerated. Xelerator X11 network processor. http://www.xelerated.com
5
 
6
R. Ennals, R. Sharp, and A. Mycroft. Linear types for packet processing. In ESOP 2004: Proceedings of the 13th European Symposium on Programming, pages 204--218, Barcelona, Spain, March 2004.
 
7
R. Ennals, R. Sharp, and A. Mycroft. Task Partitioning for Multi-core Network Processors. In Compiler Construction, volume 3443/2005 of Lecture Notes in Computer Science, pages 76--90. Springer Berlin/Heidelberg, March 2005.
8
 
9
G. Memik and W. Mangione-Smith. Nepal: A framework for efficiently structuring applications for network processors. In Proceedings of the Network Processor Workshop in conjunction with 9th International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, California, February 2003.
10
 
11
O. Morandi, F. Risso, M. Baldi, and A. Baldini. Enabling flexible packet filtering through dynamic code generation. In ICC 2008: Proceedings of the IEEE International Conference on Communications, Beijing, China, May 2008.
 
12
13
 
14
O. Morandi, F. Risso, P. Rolando, O. Hagsand, and P. Ekdahl. Mapping Packet Processing Applications on a Systolic Array Network Processor. In HPSR 2008: Proceedings of the IEEE 2008 International Conference on High Performance Switching and Routing, Shanghai, China, May 2008
15
16
17
18
 
19
A. Korobeynikov. Improving switch lowering for the llvm compiler system. In SYRCoSE 2007: Proceedings of the 2007 Spring Young Researchers Colloquium on Software Engineering, Moscow, Russia, May 2007.
20
 
21
O. Morandi, P. Monclus, G. Moscardi, and F. Risso. An intrusion detection sensor for the netvm virtual processor. Technical report, Politecnico di Torino, September 2007. TR-DAUIN-NG-02

Collaborative Colleagues:
Olivier Morandi: colleagues
Fulvio Risso: colleagues
Silvio Valenti: colleagues
Paolo Veglia: colleagues