ACM Home Page
Please provide us with feedback. Feedback
Energy efficient streaming applications with guaranteed throughput on MPSoCs
Full text PdfPdf (547 KB)
Source
International Conference On Embedded Software archive
Proceedings of the 8th ACM international conference on Embedded software table of contents
Atlanta, GA, USA
SESSION: Power table of contents
Pages 119-128  
Year of Publication: 2008
ISBN:978-1-60558-468-3
Authors
Jun Zhu  Royal Institute of Technology, Stockholm, Sweden
Ingo Sander  Royal Institute of Technology, Stockholm, Sweden
Axel Jantsch  Royal Institute of Technology, Stockholm, Sweden
Sponsors
ACM: Association for Computing Machinery
SIGBED: ACM Special Interest Group on Embedded Systems
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 10,   Downloads (12 Months): 98,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1450058.1450075
What is a DOI?

ABSTRACT

In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The public domain simulators Sim-Panalyzer and Cacti are used to estimate the energy dissipations of the parameterized architectural components. As the main contributions, we schedule the streaming applications on a multi-clock synchronous modeling framework, guarantee the application timing properties by throughput analysis, and customize both processor voltage-frequency levels and memory sizes in the design space to optimize the application pipeline parallelism for energy efficiency. Two widely used heuristic algorithms (i.e., greedy and taboo search) are used during the design optimization process. Our experiments show an energy reduction of 21% without any loss in application throughput compared with an ad-hoc approach.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
ARM Ltd. http://www.arm.com.
 
2
The SimpleScalar-RM power modeling project. http://www.eecs.umich.edu/~panalyzer/.
3
 
4
F. Boussinot and R. De Simone. The ESTEREL language. Proceedings of the IEEE, 79(9):1293--1304, September 1991.
 
5
D. Cvijovic and J. Klinowski. Taboo Search: An Approach to the Multiple Minima Problem. Science, 267:664--666, Feb. 1995.
 
6
 
7
C. Erbas. System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures. PhD thesis, 2006.
8
 
9
 
10
P. L. Guernic, J. Talpin, and J. L. Lann. Polychrony for system design. Journal of Circuits, Systems and Computers. Special Issue on Application Specific Hardware Design, 2002.
 
11
N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud. The synchronous data flow programming language LUSTRE. Proceedings of the IEEE, 79(9):1305--1320, September 1991.
12
 
13
A. Jantsch and I. Sander. Models of computation and languages for embedded system design. In IEE Proceedings on Computers and Digital Techniques, pages 114--129, 2005.
 
14
P. Le Guernic, T. Gautier, M. Le Borgne, and C. Le Marie. Programming real-time applications with SIGNAL. Proceedings of the IEEE, 79(9):1321--1335, September 1991.
 
15
 
16
E. A. Lee and T. M. Parks. Dataflow process networks. IEEE Proceedings, 83(5):773--799, May 1995.
 
17
E. A. Lee and A. Sangiovanni-Vincentelli. A framework for comparing models of computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(12):1217--1229, December 1998.
 
18
 
19
I. Sander and A. Jantsch. System modeling and transformational design refinement in ForSyDe. IEEE Trans. on CAD of Integrated Circuits and Systems, 23(1):17--32, 2004.
 
20
21
 
22
 
23
S. J. Wilton and N. P. Jouppi. Cacti: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31(5):677--688, 1996.

Collaborative Colleagues:
Jun Zhu: colleagues
Ingo Sander: colleagues
Axel Jantsch: colleagues