An out-of-order superscalar processor with speculative execution and fast, precise interrupts

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

An out-of-order superscalar processor with speculative execution and fast, precise interrupts

Full text

Pdf (1.07 MB)

Source

International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents

Portland, Oregon, United States

Pages: 272 - 281

Year of Publication: 1992

ISBN:0-8186-3175-9

Also published in ...

Authors

Harry Dwyer
H. C. Torng

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 46, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/144953.145834 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R D Acosta , J Kjelstrup , H C Torng, An instruction issuing approach to enhancing performance in multiple functinal unit processors, IEEE Transactions on Computers, v.35 n.9, p.815-828, Sept. 1986 [doi>10.1109/TC.1986.1676841]
	2	Harry Dwyer, III, Multiple, out-of-order, instruction issuing system for superscalar processors, Cornell University, Ithaca, NY, 1992
	3	W.-M. W. Hwu , Y. N. Patt, Checkpoint repair for high-performance out-of-order execution machines, IEEE Transactions on Computers, v.36 n.12, p.1496-1514, Dec. 1987 [doi>10.1109/TC.1987.5009500]
	4	Robert M. Keller, Look-Ahead Processors, ACM Computing Surveys (CSUR), v.7 n.4, p.177-195, Dec. 1975 [doi>10.1145/356654.356657]
	5	J.K.F. Lee and A.J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design". IEEE Computer, Jan. 1984, pp. 6-22.
	6	S. McFarling , J. Hennesey, Reducing the cost of branches, Proceedings of the 13th annual international symposium on Computer architecture, p.396-403, June 02-05, 1986, Tokyo, Japan
	7	James E. Smith , Andrew R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers, v.37 n.5, p.562-573, May 1988 [doi>10.1109/12.4607]
	8	Gurindar S. Sohi, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers, v.39 n.3, p.349-359, March 1990 [doi>10.1109/12.48865]
	9	G.S. Tjaden and M.J. Flynn, "Detection and Parallel Execution of Independent Instructions". IEEE Transactions on Computers, Vol. C-19, Oct. 1970, pp. 889- 895.

CITED BY 3

	Srikanth T. Srinivasan , Alvin R. Lebeck, Load latency tolerance in dynamically scheduled processors, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.148-159, November 1998, Dallas, Texas, United States
	Mayan Moudgill , Keshav Pingali , Stamatis Vassiliadis, Register renaming and dynamic speculation: an alternative approach, Proceedings of the 26th annual international symposium on Microarchitecture, p.202-213, December 01-03, 1993, Austin, Texas, United States
	Prasad N. Golla , Eric C. Lin, A dynamic scheduling logic for exploiting multiple functional units in single chip multithreaded architectures, Proceedings of the 1999 ACM symposium on Applied computing, p.466-473, February 28-March 02, 1999, San Antonio, Texas, United States