Performance evaluation of instruction scheduling on the IBM RISC System/6000

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Performance evaluation of instruction scheduling on the IBM RISC System/6000

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International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents

Portland, Oregon, United States

Pages: 226 - 235

Year of Publication: 1992

ISBN:0-8186-3175-9

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Authors

David Bernstein
Doron Cohen
Yuval Lavon
Vladimir Rainish

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 19, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	David Bernstein , Izidor Gertner, Scheduling expressions on a pipelined processor with a maximal delay of one cycle, ACM Transactions on Programming Languages and Systems (TOPLAS), v.11 n.1, p.57-66, Jan. 1989 [doi>10.1145/59287.59291]
	2	David Bernstein , Michael Rodeh, Global instruction scheduling for superscalar machines, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.241-255, June 24-28, 1991, Toronto, Ontario, Canada
	3	David Bernstein , Michael Rodeh , Mooly Sagiv, Proving safety of speculative load instructions at compile-time, Symposium proceedings on 4th European symposium on programming, p.56-72, January 1992, Rennes, France
	4	Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, Proceedings of the 18th annual international symposium on Computer architecture, p.266-275, May 27-30, 1991, Toronto, Ontario, Canada
	5	K. Ebcioğlu , Toshio Nakatani, A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture, Selected papers of the second workshop on Languages and compilers for parallel computing, p.213-229, May 1990, Urbana, Illinois, United States
	6	John R. Ellis, Bulldog: a compiler for vliw architectures (parallel computing, reduced-instruction-set, trace scheduling, scientific), 1985
	7	Jeanne Ferrante , Karl J. Ottenstein , Joe D. Warren, The program dependence graph and its use in optimization, ACM Transactions on Programming Languages and Systems (TOPLAS), v.9 n.3, p.319-349, July 1987 [doi>10.1145/24039.24041]
	8	J. Fisher. Trace scheduling' A technique for global microcode compaction. IEEE Transactions on Computers, 30(7):478-490, 1981.
	9	J. Fisher. The VLIW machine: A multiprocessor for compiling scientific code. IEEE Computer, 17(7):45- 53, 1984.
	10	Philip B. Gibbons , Steven S. Muchnick, Efficient instruction scheduling for a pipelined architecture, Proceedings of the 1986 SIGPLAN symposium on Compiler construction, p.11-16, June 25-27, 1986, Palo Alto, California, United States
	11	M. C. Golumbic , V. Rainish, Instruction scheduling beyond basic blocks, IBM Journal of Research and Development, v.34 n.1, p.93-97, Jan. 1990
	12	G.F. Grohoski, J.A.Kahle, L.E. Thatcher, and C.R. Moore. Branch and fixed-point instruction execution units. In IBM RISC System/6000 Technology, pages 24-32. IBM SA23-2619, 1990.
	13	R.D. Groves and R. Oehler. An IBM second generation RISC processor architecture. In IEEE Con/erence on Computer Design, pages 134-137, 1989.
	14	Rajiv Gupta , Mary Lou Soffa, Region Scheduling: An Approach for Detecting and Redistributing Parallelism, IEEE Transactions on Software Engineering, v.16 n.4, p.421-431, April 1990 [doi>10.1109/32.54294]
	15	C. Brian Hall , Kevin O'Brien, Performance characteristics of architectural features of the IBM RISC System/6000, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.303-309, April 08-11, 1991, Santa Clara, California, United States
	16	John L. Hennessy , Thomas Gross, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages and Systems (TOPLAS), v.5 n.3, p.422-448, July 1983 [doi>10.1145/2166.357217]
	17	M. Lam, Software pipelining: an effective scheduling technique for VLIW machines, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.318-328, June 20-24, 1988, Atlanta, Georgia, United States
	18	M. Misra, editor. IBM RISC System/6000 Technology. IBM SA23-2619, 1990.
	19	Alexandru Nicolau, Percolation Scheduling: A Parallel Compilation Technique, Cornell University, Ithaca, NY, 1985
	20	K. O'Brien, B. Hay, J. Minish, H. Schaffer, B. Schloss, A. Shepherd, and M. Zaleski. Advanced compiler technology for the RISC System/6000 architecture. In iBM RISC System/6000 Technology, pages 154-161. IBM SA23-2619, 1990.
	21	K.V. Palem and B. Simons. Scheduling time-critical instructions on risc machines. Technical Report R- :17852, IBM Research Division, 1990.
	22	David A. Patterson, Reduced instruction set computers, Communications of the ACM, v.28 n.1, p.8-21, Jan. 1985 [doi>10.1145/2465.214917]
	23	Michael D. Smith , Monica S. Lam , Mark A. Horowitz, Boosting beyond static scheduling in a superscalar processor, Proceedings of the 17th annual international symposium on Computer Architecture, p.344-354, May 28-31, 1990, Seattle, Washington, United States
	24	SPEC newsletter. Systems Per}ormance Evaluation Cooperative, 1(1), 1989.
	25	Chriss Stephens , Bryce Cogswell , John Heinlein , Gregory Palmer , John P. Shen, Instruction level profiling and evaluation of the IBM/6000, Proceedings of the 18th annual international symposium on Computer architecture, p.180-189, May 27-30, 1991, Toronto, Ontario, Canada
	26	H. S. Warren, Jr., Instruction scheduling for the IBM RISC System/6000 processor, IBM Journal of Research and Development, v.34 n.1, p.85-92, Jan. 1990
	27	AIX XL FORTRAN Compiler/6000 User's Guide. IBM SC09-1354-01, 1991.

CITED BY 4

	Ko-Yang Wang, Precise compile-time performance prediction for superscalar-based computers, ACM SIGPLAN Notices, v.29 n.6, p.73-84, June 1994
	Mark Smotherman , Shuchi Chawla , Stan Cox , Brian Malloy, Instruction scheduling for the Motorola 88110, Proceedings of the 26th annual international symposium on Microarchitecture, p.257-262, December 01-03, 1993, Austin, Texas, United States
	Steven S. Muchnick , Phillip B. Gibbons, Efficient instruction scheduling for a pipelined architecture, ACM SIGPLAN Notices, v.39 n.4, April 2004
	Abraham Mendlson , Shlomit S. Pinter , Ruth Shtokhamer, Compile time instruction cache optimizations, ACM SIGARCH Computer Architecture News, v.22 n.1, p.44-51, March 1994