Performance evaluation of instruction scheduling on the IBM RISC System/6000

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Performance evaluation of instruction scheduling on the IBM RISC System/6000

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International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents

Portland, Oregon, United States

Pages: 226 - 235

Year of Publication: 1992

ISBN:0-8186-3175-9

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Authors

David Bernstein
Doron Cohen
Yuval Lavon
Vladimir Rainish

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 15, Downloads (12 Months): 29, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 4

	Ko-Yang Wang, Precise compile-time performance prediction for superscalar-based computers, ACM SIGPLAN Notices, v.29 n.6, p.73-84, June 1994
	Mark Smotherman , Shuchi Chawla , Stan Cox , Brian Malloy, Instruction scheduling for the Motorola 88110, Proceedings of the 26th annual international symposium on Microarchitecture, p.257-262, December 01-03, 1993, Austin, Texas, United States
	Steven S. Muchnick , Phillip B. Gibbons, Efficient instruction scheduling for a pipelined architecture, ACM SIGPLAN Notices, v.39 n.4, April 2004
	Abraham Mendlson , Shlomit S. Pinter , Ruth Shtokhamer, Compile time instruction cache optimizations, ACM SIGARCH Computer Architecture News, v.22 n.1, p.44-51, March 1994