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MISC: a Multiple Instruction Stream Computer
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Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 193 - 196  
Year of Publication: 1992
ISBN:0-8186-3175-9
Also published in ...
Authors
Gary Tyson
Matthew Farrens
Andrew R. Pleszkun
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 6,   Citation Count: 11
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

BeDa91
Manuel E. Benitez , Jack W. Davidson, Code generation for streaming: an access/execute mechanism, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.132-141, April 08-11, 1991, Santa Clara, California, United States
 
CGKP87
G. L. Craig , J. R. Goodman , R. H. Katz , A. R. Pleszkun , K. Ramachandran , J. Sayah , J. E. Smith, PIPE: a high performance VLSI processor implementation, Advances in VLSI and Computer Systems, v.2 n.1-2, p.1-22, June 1987
 
FaPl91
M. Farrens and A. Pleszkun, "Overview of the PIPE Processor Implementation", Proceedings of the 24th Annual Hawaii International Conference on System Sciences, Kapaa, Kauai (January 9-11, 1991), pp. 433-443.
GHLP85
J. R. Goodman , Jian-tu Hsieh , Koujuch Liou , Andrew R. Pleszkun , P. B. Schechter , Honesty C. Young, PIPE: a VLSI decoupled architecture, Proceedings of the 12th annual international symposium on Computer architecture, p.20-27, June 17-19, 1985, Boston, Massachusetts, United States
 
McMa84
F. H. McMahon, LLNL FORTRAN KERNELS: MFLOPS, Lawrence Livermore Laboratories, Livermore, California, (March 1984).

CITED BY  11
Narayan Ranganathan , Manoj Franklin, An empirical study of decentralized ILP execution models, ACM SIGPLAN Notices, v.33 n.11, p.272-281, Nov. 1998
Jack L. Lo , Joel S. Emer , Henry M. Levy , Rebecca L. Stamm , Dean M. Tullsen , S. J. Eggers, Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading, ACM Transactions on Computer Systems (TOCS), v.15 n.3, p.322-354, Aug. 1997
Joan-Manuel Parcerisa , Antonio Gonzalez, Improving Latency Tolerance of Multithreading through Decoupling, IEEE Transactions on Computers, v.50 n.10, p.1084-1094, October 2001
Michael Sung , Ronny Krashinsky , Krste Asanović, Multithreading decoupled architectures for complexity-effective general purpose computing, ACM SIGARCH Computer Architecture News, v.29 n.5, December 2001
Barton J. Sano , Alvin M. Despain, The 16-fold way: a microparallel taxonomy, Proceedings of the 26th annual international symposium on Microarchitecture, p.60-69, December 01-03, 1993, Austin, Texas, United States
Gary Tyson , Matthew Farrens, Techniques for extracting instruction level parallelism on MIMD architectures, Proceedings of the 26th annual international symposium on Microarchitecture, p.128-137, December 01-03, 1993, Austin, Texas, United States
Avi Mendelson , Michael Bekerman, Design Alternatives of Multithreaded Architecture, International Journal of Parallel Programming, v.27 n.3, p.161-193, June 1999
Pradeep K. Dubey , Kevin O'Brien , Kathryn M. O'Brien , Charles Barton, Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grained multithreading, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, p.109-121, June 27-29, 1995, Limassol, Cyprus
Won W. Ro , Stephen P. Crago , Alvin M. Despain , Jean-Luc Gaudiot, Design and evaluation of a hierarchical decoupled architecture, The Journal of Supercomputing, v.38 n.3, p.237-259, December 2006
Richard A. Hankins , Gautham N. Chinya , Jamison D. Collins , Perry H. Wang , Ryan Rakvic , Hong Wang , John P. Shen, Multiple Instruction Stream Processor, ACM SIGARCH Computer Architecture News, v.34 n.2, p.114-127, May 2006
Won W. Ro , Jean-Luc Gaudiot, A complexity-effective microprocessor design with decoupled dispatch queues and prefetching, Parallel Computing, v.35 n.5, p.255-268, May, 2009

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

Additional Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
      B.1.5 Microcode Applications
          Subjects: Instruction set interpretation
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.1 Design Styles
          Subjects: Parallel

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Parallel processors**


General Terms:
Design, Performance

Collaborative Colleagues:
Gary Tyson: colleagues
Matthew Farrens: colleagues
Andrew R. Pleszkun: colleagues
This Article has also been published in:

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