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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Fisher, J.A. Trace scheduling: a technique for global microcode compaction. IEEE Transactions on Computers C- 30, 7 (1981).
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Foster, C.C., and Riseman, E.M. Percolation of code to enhance parallel dispatching and execution. IEEE Transactions on Computers C-21, 12 (1972), 1411-1415.
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Scott A. Mahlke , William Y. Chen , Wen-mei W. Hwu , B. Ramakrishna Rau , Michael S. Schlansker, Sentinel scheduling for VLIW and superscalar processors, Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, p.238-247, October 12-15, 1992, Boston, Massachusetts, United States
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Nicolau, A., and Fisher, J.A. Measuring the parallelism available for very long instruction word architectures. IEEE Transactions on Comp,ters C-33.
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B. R. Rau , M. Lee , P. P. Tirumalai , M. S. Schlansker, Register allocation for software pipelined loops, Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation, p.283-299, June 15-19, 1992, San Francisco, California, United States
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Rau, B.R., Schlansker, M.S., and Tirumalai, P.P. Code generation schemas for modulo scheduled DO-loops and Laboratories, 1992.
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B. Ramakrishna Rau , David W. L. Yen , Wei Yen , Ross A. Towie, The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs, Computer, v.22 n.1, p.12-26, 28-30, 32-35, January 1989
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Riseman, E.M., and Foster, C.C. The inhibition of potential parallelism by conditional jumps, iEEE Transactions on Computers C-21, 12 (1972), 1405-1411.
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Tjaden, G.S., and Flynn, M.J. Detection and parallel execution OI pigasiel iu~tructlun~, tg~,f-, Transactions on Computers C-19 10 (1970), 889-895.
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CITED BY 35
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Qingfeng Zhuge , Bin Xiao , Zili Shao , Edwin H.-M. Sha , Chantana Chantrapornchai, Optimal code size reduction for software-pipelined and unfolded loops, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
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R. Govindarajan , Erik R. Altman , Guang R. Gao, Minimizing register requirements under resource-constrained rate-optimal software pipelining, Proceedings of the 27th annual international symposium on Microarchitecture, p.85-94, November 30-December 02, 1994, San Jose, California, United States
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Michael Schlansker , Vinod Kathail , Sadun Anik, Height reduction of control recurrences for ILP processors, Proceedings of the 27th annual international symposium on Microarchitecture, p.40-51, November 30-December 02, 1994, San Jose, California, United States
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Zili Shao , Qingfeng Zhuge , Meilin Liu , Chun Xue , Edwin H. M. Sha , Bin Xiao, Algorithms and analysis of scheduling for loops with minimum switching, International Journal of Computational Science and Engineering, v.2 n.1/2, p.88-97, June 2006
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Hongbo Rong , Alban Douillet , R. Govindarajan , Guang R. Gao, Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, p.175, March 20-24, 2004, Palo Alto, California
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Qingfeng Zhuge , Chun Jason Xue , Meikang Qiu , Jingtong Hu , Edwin H. -M. Sha, Timing optimization via nest-loop pipelining considering code size, Microprocessors & Microsystems, v.32 n.7, p.351-363, October, 2008
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Meikang Qiu , Meiqin Liu , Hao Li , Hung-Chung Huang , Wenyuan Li , Jiande Wu, Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture, Journal of Signal Processing Systems, v.57 n.3, p.363-379, December 2009
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