Y-Pipe

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Y-Pipe: a conditional branching scheme without pipeline delays

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International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents

Portland, Oregon, United States

Pages: 125 - 128

Year of Publication: 1992

ISBN:0-8186-3175-9

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Authors

Michael J. Knieser
Christos A. Papachristou

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	Lilja 88	David J. Lilja, Reducing the Branch Penalty in Pipelined Processors, Computer, v.21 n.7, p.47-55, July 1988 [doi>10.1109/2.68]
	McFHen 86	S. McFarling , J. Hennesey, Reducing the cost of branches, Proceedings of the 13th annual international symposium on Computer architecture, p.396-403, June 02-05, 1986, Tokyo, Japan
	DitMcL 87	D. R. Ditzel , H. R. McLellan, Branch folding in the CRISP microprocessor: reducing branch delay to zero, Proceedings of the 14th annual international symposium on Computer architecture, p.2-8, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30351]
	Smith 81	James E. Smith, A study of branch prediction strategies, Proceedings of the 8th annual symposium on Computer Architecture, p.135-148, May 12-14, 1981, Minneapolis, Minnesota, United States
	HenPat 90	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	HwaBri 84	Kai Hwang , Faye A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, Inc., New York, NY, 1990
	SmiPle 88	James E. Smith , Andrew R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers, v.37 n.5, p.562-573, May 1988 [doi>10.1109/12.4607]
	LeeSmi 84	J. K. Lee and A. J. Smith, "Branch prediction strategies and branch target buffer design," IEEE Computers, January 1984, pp. 6-22.
	Dietz 91	I~I. Dietz, "introduction To Compilers And Translation Engineering," EE495D Course Notes, School of Electrical Engineering, Purdue University, August 1991 Revision, pp. 24-33.
	Lee 90	C. S. G. Lee, EE495M:Vision, School of Electrical Engineering, Purdue University, 1990, pp. 6-22.
	KniPapa 92	M. J. Knieser and C. A. Papachristou, "Y- Pipe: An uninterruptable conditional branching scheme," Technical Report No. CES 92-12, Department of Computer Engineering and Science, Case Western Reserve University, 1992.

CITED BY 4

	Nathalie Drach , André Seznec, MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines, Proceedings of the 26th annual international symposium on Microarchitecture, p.193-201, December 01-03, 1993, Austin, Texas, United States
	Barton J. Sano , Alvin M. Despain, The 16-fold way: a microparallel taxonomy, Proceedings of the 26th annual international symposium on Microarchitecture, p.60-69, December 01-03, 1993, Austin, Texas, United States
	Artur Klauser , Abhijit Paithankar , Dirk Grunwald, Selective eager execution on the PolyPath architecture, ACM SIGARCH Computer Architecture News, v.26 n.3, p.250-259, June 1998
	Chen-Yong Cher , T. N. Vijaykumar, Skipper: a microarchitecture for exploiting control-flow independence, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas