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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/75277.75280]
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CITED BY 44
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Nicolas Gloy , Michael D. Smith , Cliff Young, Performance issues in correlated branch prediction schemes, Proceedings of the 28th annual international symposium on Microarchitecture, p.3-14, November 29-December 01, 1995, Ann Arbor, Michigan, United States
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Jared Stark , Paul Racunas , Yale N. Patt, Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.34-43, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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Eric Hao , Po-Yung Chang , Marius Evers , Yale N. Patt, Increasing the instruction fetch rate via block-structured instruction set architectures, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.191-200, December 02-04, 1996, Paris, France
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Sumit Gupta , Nick Savoiu , Nikil Dutt , Rajesh Gupta , Alex Nicolau, Conditional speculation and its effects on performance and area for high-level snthesis, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
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R. Govindarajan , Erik R. Altman , Guang R. Gao, Minimizing register requirements under resource-constrained rate-optimal software pipelining, Proceedings of the 27th annual international symposium on Microarchitecture, p.85-94, November 30-December 02, 1994, San Jose, California, United States
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Yaw Fann , Minjoong Rim , Rajiv Jain, Global scheduling for high-level synthesis applications, Proceedings of the 31st annual conference on Design automation, p.542-546, June 06-10, 1994, San Diego, California, United States
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Michael Schlansker , Vinod Kathail , Sadun Anik, Height reduction of control recurrences for ILP processors, Proceedings of the 27th annual international symposium on Microarchitecture, p.40-51, November 30-December 02, 1994, San Jose, California, United States
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Michael Schlansker , Thomas M. Conte , James Dehnert , Kemal Ebcioglu , Jesse Z. Fang , Carol L. Thompson, Compilers for Instruction-Level Parallelism, Computer, v.30 n.12, p.63-69, December 1997
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INDEX TERMS
Primary Classification:
B.
Hardware
B.5
REGISTER-TRANSFER-LEVEL IMPLEMENTATION
B.5.1
Design
Subjects:
Styles (e.g., parallel, pipeline, special-purpose)
Additional Classification:
B.
Hardware
B.1
CONTROL STRUCTURES AND MICROPROGRAMMING
B.1.4
Microprogram Design Aids
Subjects:
Languages and compilers
C.
Computer Systems Organization
C.0
GENERAL
Subjects:
Instruction set design (e.g., RISC, CISC, VLIW)
F.
Theory of Computation
F.2
ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
F.2.2
Nonnumerical Algorithms and Problems
Subjects:
Sequencing and scheduling
General Terms:
Algorithms,
Performance
Keywords:
VLIW,
compile-time parallelization,
instruction-level parallelism,
superscalar
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