An architectural framework for migration from CISC to higher performance platforms

ABSTRACT

We describe a novel architectural framework that allows software applications written for a given Complex Instruction Set Computer (CISC) to migrate to a different, higher performance architecture, without a significant investment on the part of the application user or developer. The framework provides a hardware mechanism for seamless switching between two instruction sets, resulting in a machine that enhances application performance while keeping the same program behavior (from a user perspective). High execution speed on migrated applications is achieved through automated translation of the object code of one machine to that of the other, using advanced global optimization and scheduling techniques. Issues affecting application behavior, such as precise exceptions, as well as self-modifying code, are addressed. Relaxation of full compatibility on these issues lead to further possible performance gains, encouraging applications to adopt the newer architecture. The proposed framework offers a path for moving from complex instruction set computers (CISCs) to newer architectures, such as reduced instruction set computers (RISCs), superscalars, or very long instruction word (VLIW) machines, while protecting the extensive economic investment represented by existing software. To illustrate our approach, we show how system code written (and compiled) for the IBM System/390 can yield fine-grain parallelism, as it is targeted for execution by a VLIW machine, with encouraging performance results.

REFERENCES

• 1: Agerwala, T. and Cocke, J., "ttigh Performance Reduced Instruction Set Computers," Research Report RC-12434, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 1987.
• 2: Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
• 3: Dileep Bhandarkar , Douglas W. Clark, Performance from architecture: comparing a RISC and a CISC with similar hardware organization, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.310-319, April 08-11, 1991, Santa Clara, California, United States
• 4: Robert P. Colwell , Robert P. Nix , John J. O'Donnell , David B. Papworth , Paul K. Rodman, A VLIW architecture for a trace scheduling compiler, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.180-192, October 1987, Palo Alto, California, United States
• 5: Ebcioglu, K., "Some Design Ideas for a VLIW Architecture for Sequential Natured Software," in Parallel Processing (Proceedings of IFIP WG 10.3 Working Conference on Parallel Processing), M. Cosnard et al. (eds.), pp. 3-21, North HollandL, 1988.
• 6: Ebcioglu, K. and Groves, R., "Some Global Compiler Optimizations and Architectural Features for Improving Performance of Superscalars," Research Report RC-16145, IBM T.J. Watson Research Center, 1990.
• 7: K. Ebcioğlu , Toshio Nakatani, A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture, Selected papers of the second workshop on Languages and compilers for parallel computing, p.213-229, May 1990, Urbana, Illinois, United States
• 8: John R. Ellis, Bulldog: a compiler for VLSI architectures, MIT Press, Cambridge, MA, 1986
• 9: Emma, P.G., Knight, J.W., Pomerene, J.H., Rechtschaffen, R.N., and Sparacio, F.J., "Posting out-of-sequence fetches," United States Patent 4,991,090, February 1991.
• 10: W.-M. W. Hwu , Y. N. Patt, Checkpoint repair for high-performance out-of-order execution machines, IEEE Transactions on Computers, v.36 n.12, p.1496-1514, Dec. 1987 [doi>10.1109/TC.1987.5009500]
• 11: IBM Corporation, IBM RISC System/6000 Technology, Publication number SA23-2619, Mechanicsburg, PA, 1990.
• 12: IBM Corporation, ESA}390 Principles of Operation, Manual no. SA22-7201, Mechanicsburg, PA.
• 13: R. H. Katz , S. J. Eggers , D. A. Wood , C. L. Perkins , R. G. Sheldon, Implementing a cache consistency protocol, Proceedings of the 12th annual international symposium on Computer architecture, p.276-283, June 17-19, 1985, Boston, Massachusetts, United States
• 14: Toshio Nakatani , Kemal Ebcioğlu, Using a lookahead window in a compaction-based parallelizing compiler, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.57-68, November 27-29, 1990, Orlando, Florida, United States
• 15: Alexandru Nicolau, Percolation Scheduling: A Parallel Compilation Technique, Cornell University, Ithaca, NY, 1985
• 16: Alexandru Nicolau, Run-time disambiguation: coping with statically unpredictable dependencies, IEEE Transactions on Computers, v.38 n.5, p.633-678, May 1989
• 17: James E. Smith , Andrew R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers, v.37 n.5, p.562-573, May 1988 [doi>10.1109/12.4607]
• 18: Gurindar S. Sohi, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers, v.39 n.3, p.349-359, March 1990 [doi>10.1109/12.48865]
• 19: Warren, .S.H., Auslander, M.A., Chaitin, G.J., Chibib, A.C., Hopkins, M.E., and MacKay, A.L., "Final Code Generation in tile PL.8 Compiler," Research Report RC-11974, IBM Thomas J. Watson Research Center, 1986.
• 20: Wegman, M.N., "Fast Emulation with Compiled Look-Aside Information," Research Report RC-7580, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 1979.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.1 Large and Medium ("Mainframe") Computers
          Subjects: Super (very large) computers

General Terms:
Design, Performance