PAM: a novel performance/power aware meta-scheduler for multi-core systems

ABSTRACT

Sharing resources such as caches and main memory bandwidth in multi-core systems requires a more sophisticated scheduling scheme. PAM is a low-overhead, user-level meta-scheduler which does not require any hardware or software changes. In particular, it operates by detecting resource congestions and providing guidelines to the standard system scheduler by limiting the assignment of processes to subsets of available cores. PAM contains a cache model that it uses to predict the impact of new schedules. PAM can be used to improve the system along three dimensions: performance, power, and energy consumption (and any combination of these three). On our prototype, we show individual benchmarks can improve by up to 33% and the overall system performance can be improved by as much as 14%.

REFERENCES

• 1: "Perfmon2: The Hardware-based Performance Monitoring Interface for Linux," 2008, http://perfmon2.sourceforge.net/.
• 2: Intel Corporation, "Intel 64 and ia-32 architectures software developers manual, volume 3b: System programming guide, part 2," May 2007.
• 3: Alaa R. Alameldeen , David A. Wood, IPC Considered Harmful for Multiprocessor Workloads, IEEE Micro, v.26 n.4, p.8-17, July 2006 [doi>10.1109/MM.2006.73]
• 4: IBM Corporation, "IBM PowerExecutive," 2008, http://www.ibm.com/systems/management/director/extensions/powerexec.html.
• 5: Charles Lefurgy , Xiaorui Wang , Malcolm Ware, Server-Level Power Control, Proceedings of the Fourth International Conference on Autonomic Computing, p.4, June 11-15, 2007 [doi>10.1109/ICAC.2007.35]
• 6: "CPUSET Filesystem," 2008, http://www.bullopensource.org/cpuset/csfs.html.
• 7: Bruce L. Jacob , Peter M. Chen , Seth R. Silverman , Trevor N. Mudge, An Analytical Model for Designing Memory Hierarchies, IEEE Transactions on Computers, v.45 n.10, p.1180-1194, October 1996 [doi>10.1109/12.543711]
• 8: Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
• 9: G. Edward Suh , Srinivas Devadas , Larry Rudolph, A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.117, February 02-06, 2002
• 10: G. E. Suh , L. Rudolph , S. Devadas, Dynamic Partitioning of Shared Cache Memory, The Journal of Supercomputing, v.28 n.1, p.7-26, April 2004 [doi>10.1023/B:SUPE.0000014800.27383.8f]
• 11: Lisa R. Hsu , Steven K. Reinhardt , Ravishankar Iyer , Srihari Makineni, Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA [doi>10.1145/1152154.1152161]
• 12: Nauman Rafique , Won-Taek Lim , Mithuna Thottethodi, Architectural support for operating system-driven CMP cache management, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA [doi>10.1145/1152154.1152160]
• 13: Allan Snavely , Dean M. Tullsen, Symbiotic jobscheduling for a simultaneous multithreaded processor, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.234-244, November 2000, Cambridge, Massachusetts, United States
• 14: Alexandra Fedorova , Margo Seltzer , Christoper Small , Daniel Nussbaum, Performance of multithreaded chip multiprocessors and implications for operating system design, Proceedings of the annual conference on USENIX Annual Technical Conference, p.26-26, April 10-15, 2005, Anaheim, CA
• 15: Alexandra Fedorova , Margo Seltzer , Michael D. Smith, Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler, Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, p.25-38, September 15-19, 2007 [doi>10.1109/PACT.2007.40]
• 16: A. Fedorova, D. Vengerov, and D. Doucette, "Operating System Scheduling on Heterogeneous Core Systems," in Proceedings of the First Workshop on Operating System Support for Heterogeneous Multicore Architectures, in conjunction with PACT, 2007.
• 17: D. Shelepov and A. Fedorova, "Scheduling on Heterogeneous Multicore Processors Using Architectural Signatures," in Proceedings of the Workshop on the Interaction between Operating Systems and Computer Architecture, in conjunction with ISCA, 2008.
• 18: Kevin M. Lepak , Harold W. Cain , Mikko H. Lipasti, Redeeming IPC as a Performance Metric for Multithreaded Programs, Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques, p.232, September 27-October 01, 2003

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.4 Parallel Architectures

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS

General Terms:
Design, Experimentation, Measurement, Performance