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Breaking the memory wall in MonetDB
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Source
Communications of the ACM archive
Volume 51 ,  Issue 12  (December 2008) table of contents
Surviving the data deluge
SECTION: Research highlights table of contents
Pages 77-85  
Year of Publication: 2008
ISSN:0001-0782
Authors
Peter A. Boncz  CWI, Kruislaan, Amsterdam, the Netherlands
Martin L. Kersten  CWI, Kruislaan, Amsterdam, the Netherlands
Stefan Manegold  CWI, Kruislaan, Amsterdam, the Netherlands
Publisher
ACM  New York, NY, USA
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ABSTRACT

In the past decades, advances in speed of commodity CPUs have far outpaced advances in RAM latency. Main-memory access has therefore become a performance bottleneck for many computer applications; a phenomenon that is widely known as the "memory wall." In this paper, we report how research around the MonetDB database system has led to a redesign of database architecture in order to take advantage of modern hardware, and in particular to avoid hitting the memory wall. This encompasses (i) a redesign of the query execution model to better exploit pipelined CPU architectures and CPU instruction caches; (ii) the use of columnar rather than row-wise data storage to better exploit CPU data caches; (iii) the design of new cache-conscious query processing algorithms; and (iv) the design and automatic calibration of memory cost models to choose and tune these cache-conscious algorithms in the query optimizer.


REFERENCES

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Boncz, P.A., Zukowski, M., and Nes, N. MonetDB/X100: Hyper-pipelining query execution. In International Conference on Innovative Data Systems Research (CIDR), Jan. 2005, 225--237.
 
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Manegold, S. Understanding, modeling, and improving main-memory database performance. PhD thesis, Universiteit van Amsterdam, Amsterdam, the Netherlands, Dec. 2002.
 
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Collaborative Colleagues:
Peter A. Boncz: colleagues
Martin L. Kersten: colleagues
Stefan Manegold: colleagues