Analog hardware implementation of a vector quantizer for focal-plane image compression

ABSTRACT

We propose the use of a low-complexity vector quantizer for coding data vectors at the focal plane of CMOS image sensors, directly from analog pixels samples prior to A/D conversion. To be suitable for focal-plane image compression applications, the encoder must have a very low transistor count. Without considering the implementation errors in DPCM preprocessing of the image data, a test image is compressed by the proposed vector quantizer with peak signal-to-noise ratio around 26 dB at 0.73 bpp. The vector quantizer requires 145 transistors for each block of 4x4 pixels, and Monte Carlo simulation results in Cadence/Spectre led to the same image compression results that had been achieved in theoretical predictions.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

Additional Classification:
  I. Computing Methodologies
  I.4 IMAGE PROCESSING AND COMPUTER VISION
      I.4.1 Digitization and Image Capture
          Subjects: Quantization

General Terms:
Design

Keywords:
CMOS analog hardware, analog image processing, vector quantization