A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter

ABSTRACT

The paper presents a new architecture for implementation of an H.264/MPEG-4 AVC deblocking filter in hardware. This architecture adopts an innovative 4-stage pipelined structure in the edge filter. The proposed approach redesigns internal filter datapaths and memory organization in order to reduce both global processing cycles per macroblock and chip area. A comparison with other previous related works indicated that the proposed architecture offers significant gains for practical implementation in embedded systems, which commonly have restrictions in power consumption, clock speed and memory capability.

REFERENCES

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Parallel circuits

General Terms:
Design, Reliability, Verification

Keywords:
H.264, deblocking filter, programmable logic, video encoder