A novel scheme to reduce short-circuit power in mesh-based clock architectures

ABSTRACT

Meshes are widely used for distributing clock in high performance designs. In the past, they were used exclusively for microprocessors, now they are being integrated into the ASIC design flow as well. A mesh has a much smaller skew and jitter, but the high power consumption limits its applicability. In this work, we address the high power consumption of mesh architectures. We propose a novel design for mesh buffers to minimize the short circuit current caused by the different arrival times of the clock signal at mesh buffer inputs. By reducing the short circuit current, we show that the mesh power consumption is reduced by up to 59% and skew by 22%.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.m Miscellaneous
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Experimentation

Keywords:
clock mesh, clock skew, power, short-circuit