A new march sequence to fit DDR SDRAM test in burst mode

ABSTRACT

This work is focused on DDR SDRAM test based on data word burst-oriented access. Existent March algorithms are not efficient to detect static unlinked faults (as Coupling and Address Decoder faults) in burst-mode operation. We propose to modify the March X algorithm to overcome its weakness. The proposed algorithm can reduce the total test time over 30% by using burst-mode data access in the DDR SDRAM test. The new algorithm has a length of (6 + BL)N, were BL is the burst-length used in data access. Results show that the proposed method detects errors produced by address decoder faults in word-oriented memories using burst mode operation, which is characteristic of DDR SDRAMs. We also propose to implement the new March algorithm into built-in self-test (BIST) modules for external memory testing.

REFERENCES

• 1: A. Bonatto, A. Borin, and A. Susin. DDR SDRAM Memory Controller Validation for FPGA Synthesis. In LATW2008: Proceedings of the 9th IEEE Latin-American Test Workshop, pages 177--182, Puebla, Mexico, Feb. 2008.
• 2: M. L. Bushnell and V. D. Agrawal. Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, page 690. Kluwer Academic, Secaucus, NJ, USA, 2002.
• 3: O. Caty, I. Bayraktaroglu, A. Majumdar, R. Lee, J. Bell, and L. Curhan. Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. In Test Conference, 2003. Proceedings. ITC 2003. International, pages 140--149, 2003.
• 4: JEDEC. JESD79: Double Data Rate (DDR) SDRAM Specification. JEDEC Solid State Technology Association, Virginia, USA, 2003.
• 5: Heon C. Kim , Hong-Shin Jun , Xinli Gu , Sung S. Chung, At-Speed Interconnect Test and Diagnosis of External Memories on a System, Proceedings of the International Test Conference on International Test Conference, p.156-162, October 26-28, 2004
• 6: Micron. Micron DDR SDRAM Products. {Online} Available: http://www.micron.com/products/dram/ddr/.
• 7: Sheng-Chih Shen , Hung-Ming Hsu , Yi-Wei Chang , Kuen-Jong Lee, A High Speed BIST Architecture for DDR-SDRAM Testing, Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing, p.52-57, August 03-05, 2005 [doi>10.1109/MTDT.2005.9]
• 8: A. van de Goor , M. Abadir , A. Carlin, Minimal Test for Coupling Faults in Word-Oriented Memories, Proceedings of the conference on Design, automation and test in Europe, p.944, March 04-08, 2002
• 9: A. J. van de Goor, Testing semiconductor memories: theory and practice, John Wiley & Sons, Inc., New York, NY, 1991
• 10: A. J. van de Goor , G. N. Gaydadjiev, An analysis of (linked) address decoder faults, Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing, p.13, August 11-12, 1997
• 11: A. J. van de Goor , I. B. S. Tlili, March tests for word-oriented memories, Proceedings of the conference on Design, automation and test in Europe, p.501-509, February 23-26, 1998, Le Palais des Congrés de Paris, France
• 12: Jöerg E. Vollrath, Testing and Characterization of SDRAMs, IEEE Design & Test, v.20 n.1, p.42-50, January 2003 [doi>10.1109/MDT.2003.1173052]
• 13: Xilinx. Xilinx Memory Solutions. {Online} Available: http://www.xilinx.com/memory.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.4 Reliability, Testing, and Fault-Tolerance**

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Design, Verification

Keywords:
DDR SDRAM, built-in self test, march algorithms, memory test, system on chip