| Metal filling impact on standard cells: definition of the metal fill corner concept |
| Full text |
Pdf
(248 KB)
|
Source
|
SBCCI
archive
Proceedings of the 21st annual symposium on Integrated circuits and system design
table of contents
Gramado, Brazil
SESSION: Design for yield
table of contents
Pages 16-21
Year of Publication: 2008
ISBN:978-1-60558-231-3
|
|
Authors
|
|
Laurent Remy
|
ATMEL Rousset, Rousset, France
|
|
Philippe Coll
|
ATMEL Rousset, Rousset, France
|
|
Fabrice Picot
|
ATMEL Rousset, Rousset, France
|
|
Philippe Mico
|
ATMEL Rousset, Rousset, France
|
|
Jean-Michel Portal
|
IM2NP UMR 6242 CNRS, Marseille, France
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 7, Downloads (12 Months): 27, Citation Count: 0
|
|
|
ABSTRACT
The objective of this paper is to evaluate the delay impact of staggered metal filling (Metal2) on the standard cells and their associated local interconnect (Metal1). A Design Of Experiment (DOE) is used to define a large range of filling pattern shapes and positions. This set of filling patterns is then inserted in a Ring Oscillator (RO). From the filled RO simulations, the RO delay is expressed as a function of the filling pattern features. The maximal timing error between the model and the simulation is 1.3%, validating the model. The filling impact on RO delay magnifies the one introduced by the front-end process variations (PV). Consequently, the filling influence is introduced for the minimal, typical and maximal corners, defined now with Process (P), Voltage (V), Temperature (T) and Filling density (F) characteristics.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
R. Chang and C. J. Spanos. Dishing-radius model of copper cmp dishing effects. Semiconductor Manufacturing, 18:297--303, May 2005.
|
| |
2
|
|
| |
3
|
|
| |
4
|
Atsushi Kurokawa , Toshiki Kanamoto , Tetsuya Ibe , Akira Kasebe , Chang Wei Fong , Tetsuro Kage , Yasuaki Inoue , Hiroo Masuda, Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills, Proceedings of the 6th International Symposium on Quality of Electronic Design, p.586-591, March 21-23, 2005
[doi> 10.1109/ISQED.2005.47]
|
| |
5
|
A. Kurokawa, T. Kanamoto, A. Kasebe, Y. Inoue, and H. Masuda. Efficient capacitance extraction method for interconnects with dummy fills. Custom Integrated Circuits Conference, pages 485--488, October 2004.
|
| |
6
|
S. Lakshminarayanan, P. J. Wright, and J. Pallinti. Electrical characterization of the copper cmp process and derivation of metal layout rules. Semiconductor Manufacturing, 16:668--676, November 2003.
|
| |
7
|
K.-H. Lee, J.-K. Park, Y.-N. Yoon, D.-H. Jung, J.-P. Shin, Y.-K. Park, and J.-T. Kong. Analyzing the effects of floating dummy-fills: from feature scaleanalysis to full-chip rc extraction. International Electron Devices Meeting, pages 31.3.1--31.3.4, 2001.
|
| |
8
|
Won-Seok Lee , Keun-Ho Lee , Jin-Kyu Park , Tae-Kyung Kim , Young-Kwan Park , Jeong-Taek Kong, Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling, Proceedings of the 4th International Symposium on Quality Electronic Design, p.373, March 24-26, 2003
|
| |
9
|
B. E. Stine, D. S. Boning, J. E. Chung, L. Camilletti, F. Kruppa, E. R. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor. The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes. Electron Devices, 45:665--679, March 1998.
|
| |
10
|
W. Yu, M. Zhang, and Z. Wang. Efficient 3-d extraction of interconnect capacitance considering floating metal fills with bondary element method. Computer-Aided Design of Integrated Circuits and Systems, 25:12--18, January 2006.
|
INDEX TERMS
Primary Classification:
G.
Mathematics of Computing
G.3
PROBABILITY AND STATISTICS
Subjects:
Probabilistic algorithms (including Monte Carlo)
Additional Classification:
B.
Hardware
B.7
INTEGRATED CIRCUITS
B.7.3
Reliability and Testing**
General Terms:
Algorithms,
Design,
Experimentation,
Measurement,
Reliability,
Theory
Keywords:
capacitance,
corners,
design of experiment,
dispersion,
interconnect,
metal filling,
modelization,
ring oscillators,
standard cells
|