Lithography friendly routing: from construct-by-correction to correct-by-construction

ABSTRACT

Deep sub-wavelength lithography, e.g., using the 193nm lithography to print 45nm, 32nm, and even 22nm integrated circuits, is one of the most fundamental limitations for the continuous CMOS scaling. Lithography printability is strongly layout dependent. Routing is the last major physical design step before tapeout, thus it plays an important role in addressing the overall circuit manufacturability and product yield. This talk will discuss some recent advancement of lithography friendly routing from post-routing hotspot fixing (construct-by-correction) to during-routing hotspot avoidance (correct-by-construction) guided by predictive post-OPC lithography metrics. We will compare the quality of results and runtime of these approaches, and show how to combine them. We will also discuss the emerging research needs, such as double patterning lithography for 32nm and 22nm nodes and how routing may cope with them.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design

Keywords:
routing