Sizing CMOS circuits by means of the gm/ID methodology and a compact model

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Sizing CMOS circuits by means of the gm/ID methodology and a compact model

Full text

Pdf (139 KB)

Source

SBCCI archive
Proceedings of the 21st annual symposium on Integrated circuits and system design table of contents

Gramado, Brazil

TUTORIAL SESSION: Tutorials table of contents

Pages 1-1

Year of Publication: 2008

ISBN:978-1-60558-231-3

Author

Paul Jespers

Université Catholique de Louvain, Louvain-la-neuve, Belgium

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 21, Downloads (12 Months): 123, Citation Count: 0

Additional Information:

abstract index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1404371.1404373 What is a DOI?

ABSTRACT

The gm/ID sizing methodology. Sizing the Intrinsic Gain Stage by means of experimental data or a model like the E.K.V./A.C.M. model. Sizing short channel devices with parameters that are functions of bias conditions. Parameter acquisition, accuracy, examples. Application to the sizing of low-power low-voltage CMOS circuits like the Miller Op. Amp, Barranco's current sources, etc.

INDEX TERMS

Primary Classification:
B. Hardware
B.7 INTEGRATED CIRCUITS
B.7.1 Types and Design Styles