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ABSTRACT

The Network-on-Chip (NoC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The next challenge is to use NoCs as the backbones of the upcoming generation of 3D chips, assembled by stacking multiple silicon layers. Multiple technical issues have to be tackled in this respect. One of the foremost is the unsuitability of a purely synchronous design style, as it is not straightforward to impose a strict bound on the clock skew among multiple clock trees across different layers. In this paper, we present a scheme to handle mesochronous communication in 3D NoCs and analyze (i) the circuit design, (ii) the timing properties, (iii) the requirements to support flow control across mesochronous links, (iv) the implementation cost of such a scheme after placement and routing.

REFERENCES

• 1: F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini. A layout-aware analysis of networks-on-chip and traditional interconnects for MPSoCs. IEEE Transactions on Computer-Aided Design, 26(3):421--434, March 2007.
• 2: F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini. A layout-aware analysis of networks-on-chip and traditional interconnects for mpsocs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(3):421--434, March 2007.
• 3: John Bainbridge , Steve Furber, Chain: A Delay-Insensitive Chip Area Interconnect, IEEE Micro, v.22 n.5, p.16-23, September 2002 [doi>10.1109/MM.2002.1044296]
• 4: E. Beigne , F. Clermidy , P. Vivet , A. Clouard , M. Renaudin, An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, p.54-63, March 14-16, 2005 [doi>10.1109/ASYNC.2005.10]
• 5: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 6: Tobias Bjerregaard , Jens Sparso, A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip, Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, p.34-43, March 14-16, 2005 [doi>10.1109/ASYNC.2005.7]
• 7: William J. Dally , Brian Towles, Route packets, not wires: on-chip inteconnection networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 8: Brett Feero , Partha Pratim Pande, Performance Evaluation for Three-Dimensional Networks-On-Chip, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, p.305-310, March 09-11, 2007 [doi>10.1109/ISVLSI.2007.79]
• 9: S. Fujita, K. Nomura, K. Abe, and T. H. Lee. 3d on-chip networking technology based on post-silicon devices for future networks-on-chip. In Nano-Networks and Workshops, pages 1--5, September 2006.
• 10: Maged Ghoneima, Yehea Ismail, Muhammad Khellah, and Vivek De. Variation-tolerant and low-power source-synchronous multicycle on-chip interconnection scheme. VLSI Design, 2007, 2007.
• 11: Eckhard Grass, Frank Winkler, Milos Krstic, Alexandra Julius, Christian Stahl, and Maxim Piz. Enhanced gals techniques for datapath applications. In PATMOS, pages 581--590, 2005.
• 12: Jongman Kim , Chrysostomos Nicopoulos , Dongkook Park , Reetuparna Das , Yuan Xie , Vijaykrishnan Narayanan , Mazin S. Yousif , Chita R. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures, Proceedings of the 34th annual international symposium on Computer architecture, June 09-13, 2007, San Diego, California, USA [doi>10.1145/1250662.1250680]
• 13: M. Krstic, E. Grass, C. Stahl, and M. Piz. System integration by request-driven gals design. IEE Proceedings on Computers and Digital Techniques, 153(5):362--372, September 2006.
• 14: D. Lattard and et al. A telecom baseband circuit-based on an asynchronous network-on-chip. In Proc. of the International Solid State Circuits Conference, ISSCC2007, pages 258--259, 2007.
• 15: Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-Wuk Lee, and Hoi-Jun Yoo. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform. In Digest of Technical Papers of the 2004 IEEE International Solid-State Circuits Conference (ISSC), pages 152--518. IEEE Computer Society, 2004.
• 16: Kangmin Lee , Se-Joong Lee , Hoi-Jun Yoo, Low-power network-on-chip for high-performance SoC design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.2, p.148-160, February 2006 [doi>10.1109/TVLSI.2005.863753]
• 17: Se-Joong Lee. Cost-optimization and chip implementation of on-chip network. Technical report, KAIST, 2005.
• 18: Andrew Lines, Asynchronous Interconnect for Synchronous SoC Design, IEEE Micro, v.24 n.1, p.32-41, January 2004 [doi>10.1109/MM.2004.1268991]
• 19: Igor Loi , Federico Angiolini , Luca Benini, Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow, Proceedings of the 2nd international conference on Nano-Networks, September 24-26, 2007, Catania, Italy
• 20: D. Mangano, R. Locatelli, A. Scandurra, C. Pistritto, M. Coppola, L. Fanucci, F. Vitullo, and D. Zandri. Skew insensitive physical links for network on chip. In 1st International Conference on Nano-Networks (NanoNet), pages 1--5, 2006.
• 21: Christopher A. Mineo. Clock tree insertion and verification for 3D integrated circuits. Technical report, North Carolina State University at Raleigh, 2005.
• 22: Mosin Mondal , Andrew J. Ricketts , Sami Kirolos , Tamer Ragheb , Greg Link , N. Vijaykrishnan , Yehia Massoud, Thermally robust clocking schemes for 3D integrated circuits, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
• 23: Srinivasan Murali , Martijn Coenen , Andrei Radulescu , Kees Goossens , Giovanni De Micheli, Mapping and configuration methods for multi-use-case networks on chips, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan [doi>10.1145/1118299.1118344]
• 24: Srinivasan Murali and et al. Designing message-dependent deadlock free networks on chips for application-specific systems on chips. In VLSI-SoC, pages 158--163, 2006.
• 25: Ethiopia Nigussie , Jouni Isoaho, Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling, Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, p.217, March 02-03, 2006 [doi>10.1109/ISVLSI.2006.34]
• 26: Robert S. Patti. Three-dimensional integrated circuits and the future of system-on-chip designs. Proceedings of the IEEE, 94(6), June 2006.
• 27: Vasilis F. Pavlidis and Eby G. Friedman. 3-D topologies for networks-on-chip. In Proceedings of the IEEE SoC Conference (SOCC), pages 285--288. IEEE Computer Society, 2006.
• 28: W. J. Bainbridge , L. A. Plana , S. B. Furber, The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip, Proceedings of the conference on Design, automation and test in Europe, p.30274, February 16-20, 2004
• 29: Dobkin (Reuven) Rostislav , Victoria Vishnyakov , Eyal Friedman , Ran Ginosar, An Asynchronous Router for Multiple Service Levels Networks on Chip, Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, p.44-53, March 14-16, 2005 [doi>10.1109/ASYNC.2005.11]
• 30: Krishnan Srinivasan , Karam S. Chatha, A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures, Proceedings of the 7th International Symposium on Quality Electronic Design, p.352-357, March 27-29, 2006 [doi>10.1109/ISQED.2006.13]
• 31: S. Spiesshoefer and et al. Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development. In Electronic Components and Technology Conference, 2004.
• 32: Mikkel B. Stensgaard , Tobias Bjerregaard , Jens Sparso , Johnny Halkjaer Pedersen, A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip, Proceedings of the 9th EUROMICRO Conference on Digital System Design, p.641-648, August 30-September 01, 2006 [doi>10.1109/DSD.2006.17]
• 33: A. W. Topol , D. C. La Tulipe, Jr. , L. Shi , D. J. Frank , K. Bernstein , S. E. Steen , A. Kumar , G. U. Singco , A. M. Young , K. W. Guarini , M. Ieong, Three-dimensional integrated circuits, IBM Journal of Research and Development, v.50 n.4/5, p.491-506, July 2006
• 34: Pascal T. Wolkotte , Philip K. F. Holzenspies , Gerard J. M. Smit, Fast, Accurate and Detailed NoC Simulations, Proceedings of the First International Symposium on Networks-on-Chip, p.323-332, May 07-09, 2007 [doi>10.1109/NOCS.2007.18]
• 35: Cesar Albenes Zeferino , Altamiro Amadeu Susin, SoCIN: A Parametric and Scalable Network-on-Chip, Proceedings of the 16th symposium on Integrated circuits and systems design, p.169, September 08-11, 2003

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Design, Performance