Thread fusion

ABSTRACT

This work proposes Thread Fusion as an effective way of reducing power consumption when a Simultaneous Multi-Threaded (SMT) core is executing two threads from a homogeneous parallel application. Two dynamic instances of the same static instruction, each from a different thread are merged (fused) into a single instruction, consuming half of the resources of front-end pipeline stages. When the fused instruction is executed, it is cloned and it proceeds at full bandwidth. Our simulation results show average energy reduction of 10% with less than 1% impact on performance.

REFERENCES

• 1: Vishal Aslot , Max J. Domeika , Rudolf Eigenmann , Greg Gaertner , Wesley B. Jones , Bodo Parady, SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance, Proceedings of the International Workshop on OpenMP Applications and Tools: OpenMP Shared Memory Parallel Programming, p.1-10, July 30-31, 2001
• 2: S.Y. Borkar. Platform 2015: Intel processor and platform evolution for the next decade. Technical report, Intel White Paper, Mar. 2005.
• 3: Anne Bracy , Amir Roth, Serialization-Aware Mini-Graphs: Performance with Fewer Resources, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.171-184, December 09-13, 2006 [doi>10.1109/MICRO.2006.45]
• 4: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 5: James Donald , Margaret Martonosi, Techniques for Multicore Thermal Management: Classification and New Exploration, Proceedings of the 33rd annual international symposium on Computer Architecture, p.78-88, June 17-21, 2006
• 6: P. Dubey. Recognition, Mining and Synthesis Moves Computers to the Era of Tera. Technology@Intel Magazine. http://www.intel.com/technology/magazine/computing/recognition-mining-synthesis-0205.htm, 2005
• 7: M. Ekman, F. Dahlgren and P.Stenstrom. "Evaluation of Snoop-Energy Reduction Techniques for Chip-Multiprocessors". Workshop on Duplicating, Deconstructing and Debunking, 2002.
• 8: Frequent Itemset Mining Implementations Repository. http://fimi.cs.helsinki.fi
• 9: S. Gochman, R. Ronnen, I. Anati, A. Berkovits, T. Kurts, A. Naveh, A. Saeed, Z. Speerber, R.C. Valentine. "The Intel Pentium M Processor: Microarchitecture and Performance". Intel Technology Journal vol 7(2), 2003.
• 10: Richard A. Hankins , Gautham N. Chinya , Jamison D. Collins , Perry H. Wang , Ryan Rakvic , Hong Wang , John P. Shen, Multiple Instruction Stream Processor, Proceedings of the 33rd annual international symposium on Computer Architecture, p.114-127, June 17-21, 2006
• 11: Intel Corp., Computer-Intensive Highly Parallel Applications and Uses. Intel Technology Journal, 9(2), May 2005.
• 12: Canturk Isci , Alper Buyuktosunoglu , Chen-Yong Cher , Pradip Bose , Margaret Martonosi, An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.347-358, December 09-13, 2006 [doi>10.1109/MICRO.2006.8]
• 13: A. Jaleel, M. Mattina and B. Jacob. "Last Level Cache (LLC) performance of data-mining workloads on a CMP - A case study of parallel bioinformatics workloads". Proc. International Symposium on high Performance Computing, 2006.
• 14: Poonacha Kongetira , Kathirgamar Aingaran , Kunle Olukotun, Niagara: A 32-Way Multithreaded Sparc Processor, IEEE Micro, v.25 n.2, p.21-29, March 2005 [doi>10.1109/MM.2005.35]
• 15: D.J. Kuck. Platform 2015 software: Enabling innovation in parallelism for the next decade. Technical report, Intel White Paper, Mar. 2005.
• 16: Jian Li , Jose F. Martinez , Michael C. Huang, The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors, Proceedings of the 10th International Symposium on High Performance Computer Architecture, p.14, February 14-18, 2004 [doi>10.1109/HPCA.2004.10018]
• 17: David López , Josep Llosa , Mateo Valero , Eduard Ayguadé, Widening resources: a cost-effective technique for aggressive ILP architectures, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.237-246, November 1998, Dallas, Texas, United States
• 18: Iván Martel , Daniel Ortega , Eduard Ayguadé , Mateo Valero, Increasing effective IPC by exploiting distant parallelism, Proceedings of the 13th international conference on Supercomputing, p.348-355, June 20-25, 1999, Rhodes, Greece [doi>10.1145/305138.305212]
• 19: Kunle Olukotun , Basem A. Nayfeh , Lance Hammond , Ken Wilson , Kunyung Chang, The case for a single-chip multiprocessor, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.2-11, October 01-04, 1996, Cambridge, Massachusetts, United States
• 20: Alex Pajuelo , Antonio González , Mateo Valero, Speculative dynamic vectorization, Proceedings of the 29th annual international symposium on Computer architecture, May 25-29, 2002, Anchorage, Alaska
• 21: J. Pisharath, Y. Liu, B. Ozisikyilmaz, R. Narayanan, W. Liao, A. Choudhary, G. Memik.. NU-MineBench Project. http://cucis.ece.northwestern.edu/projects/DMS/MineBench.html
• 22: Sun Microsystems. Throughput Computing. Technical report, Sun White Paper, Nov. 2005.
• 23: Dean M. Tullsen , Susan J. Eggers , Henry M. Levy, Simultaneous multithreading: maximizing on-chip parallelism, Proceedings of the 22nd annual international symposium on Computer architecture, p.392-403, June 22-24, 1995, S. Margherita Ligure, Italy
• 24: R.Uhlig, R.Fishtein, O. Gershon, I. Hirsh, and H. Wang. "SoftSDV: A Pre-silicon Software Development Environment for the IA-64 Architecture". Intel Technology Journal, Vol 3, Issue 4,1999.
• 25: Sriram Vajapeyam , P. J. Joseph , Tulika Mitra, Dynamic vectorization: a mechanism for exploiting far-flung ILP in ordinary programs, Proceedings of the 26th annual international symposium on Computer architecture, p.16-27, May 01-04, 1999, Atlanta, Georgia, United States

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)

General Terms:
Design, Performance

Keywords:
chip multi-processor, computer architecture, energy-aware, in-order pipeline, low-power, microarchitecture, multi-threaded application, thread fusion