Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures

ABSTRACT

Aggressive technology scaling is increasing the impact of soft errors on microprocessor reliability. Dynamic Voltage Frequency Scaling (DFVS) algorithms are conventionally studied from a performance per watt basis. But applying DVFS impacts reliability as well. Since DVFS affects the occupancy of different pipeline structures, they impact the soft error masking seen at the architectural level. Architectural Vulnerability Factors (AVF) captures this masking and in this work we study the impact of DVFS on AVF in a GALS environment. We show that the AVF of pipeline structures could vary by as much as 80% between different DVFS algorithms. Since AVF has a significant impact on the Mean Time To Failure (MTTF) of a system, these results indicate that when choosing a particular DVFS algorithm their reliability impact cannot be ignored. Hence we provide the Vulnerability Efficiency for the DVFS algorithms which captures their ability to optimize performance, power and reliability. Our results show that a Non-DVFS environment optimizes vulnerability efficiency better than any of the DVFS algorithms.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.0 General

General Terms:
Experimentation, Performance, Reliability

Keywords:
microarchitecture, multi-clocked domains, soft errors