A secure and low-energy logic style using charge recovery approach

ABSTRACT

The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks especially against differential power analysis attacks. Our approach is a modified version of a classical charge recovery logic style namely 2N-2N2P. Simulation results show a significant improvement in DPA-resistance level as well as in power consumption reduction in comparison with 2N-2N2P and other DPA-resistant logic styles.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.0 GENERAL

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.0 General
  B.7 INTEGRATED CIRCUITS
      B.7.0 General

General Terms:
Security

Keywords:
cell level DPA-countermeasure, charge recovery logic, differential power analysis, side-channel attack