A physical level study and optimization of CAM-based checkpointed register alias table

ABSTRACT

Using full-custom layouts in 130 nm technology, this work studies how the latency and energy of a checkpointed, CAM-based Register Alias Table (cRAT) vary as a function of the window size, the issue width, and the number of embedded global checkpoints (GCs). These results are compared to those of the SRAM-based RAT (sRAT). Understanding these variations is useful during the early stages of architectural exploration where physical level information is not yet available. It is found that compared to sRAT, cRAT is more sensitive to the number of physical registers and issue width, however, it is less sensitive to the number of GCs. In addition, beyond a certain number of GCs, cRAT becomes faster than its equivalent sRAT. For instance, this is true when a RAT for 64 architectural and 128 physical registers has at least 20 GCs. This work also proposes an energy optimization for the cRAT; this optimization selectively disables cRAT entries that do not result in a match during lookup. The energy savings are, for the most part, a function of the number of physical registers. For instance, for a cRAT with 128 entries energy is reduced by 40%.

REFERENCES

• 1: Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan, An analysis of a resource efficient checkpoint architecture, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.4, p.418-444, December 2004 [doi>10.1145/1044823.1044826]
• 2: Patrick Akl , Andreas Moshovos, BranchTap: improving performance with very few checkpoints through adaptive speculation control, Proceedings of the 20th annual international conference on Supercomputing, June 28-July 01, 2006, Cairns, Queensland, Australia [doi>10.1145/1183401.1183409]
• 3: A. Cristal, D. Ortega, J. Llosa and M. Valero, "Kilo-Instruction Processors", International Symposium on High Performance Computing, Oct. 2003.
• 4: A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), p.118, September 16-18, 2002
• 5: R. Heald et.al., "A Third-Generation SPARC V9 64-b Microprocessor", IEEE Journal of Solid-State Circuits, 35(11): 1526--1538, Nov. 2000.
• 6: R. E. Kessler, The Alpha 21264 Microprocessor, IEEE Micro, v.19 n.2, p.24-36, March 1999 [doi>10.1109/40.755465]
• 7: Andreas Moshovos, Checkpointing alternatives for high performance, power-aware processors, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871585]
• 8: Subbarao Palacharla , James E. Smith, Complexity-effective superscalar processors, The University of Wisconsin - Madison, 1998
• 9: Elham Safi , Patrick Akl , Andreas Moshovos , Andreas Veneris , Aggeliki Arapoyianni, On the latency, energy and area of checkpointed, superscalar register alias tables, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA [doi>10.1145/1283780.1283863]
• 10: D. Tarjan, S. Thoziyoor and N. P. Jouppi, CACTI 4.0, HP Labs Technical Report HPL-2006-86, 2006.
• 11: Kenneth C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, v.16 n.2, p.28-40, April 1996 [doi>10.1109/40.491460]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.0 General

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
checkpointing, energy, latency, register renaming