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Analytical results for design space exploration of multi-core processors employing thread migration
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International Symposium on Low Power Electronics and Design archive
Proceeding of the 13th international symposium on Low power electronics and design table of contents
Bangalore, India
POSTER SESSION: Poster session table of contents
Pages 229-232  
Year of Publication: 2008
ISBN:978-1-60558-109-5
Authors
Ravishankar Rao  Arizona State University, Tempe, AZ, USA
Sarma Vrudhula  Arizona State University, Tempe, AZ, USA
Krzysztof Berezowski  Arizona State University, Tempe, AZ, USA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Migrating threads away from the hot cores in a multicore processor allows them to operate at up to higher speeds. While this technique has already attracted a lot of research effort, the majority of thread migration studies are simulation-based. Although they are valuable for micro-architectural level optimization, they require prohibitively long simulation times, and hence have limited value for early design space exploration. We derive closed form expressions for the steady-state throughput of a multicore processor that employs thread migration and throttling for thermal management. These expressions can be evaluated under a millisecond (vs days for cycle-accurate simulation), and allow designers greater flexibility in evaluating the trade-offs involved in implementing thread migration on-chip. We also developed a system-level power/thermal simulator that we used to validate the analytical results.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Chaparro, J. Gonzalez, G. Magklis, Q. Cai, and A. Gonzalez. Understanding the thermal implications of multicore architectures. IEEE Trans. Parallel and Distributed Sys., 18(8):1055--1065, August 2007.
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W. Liao, L. He, and K. M. Lepak. Temperature and supply voltage aware performance and power modeling at microarchitecture level. IEEE Trans. Computer-Aided Design, 24(7):1042--1053, July 2005.
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Collaborative Colleagues:
Ravishankar Rao: colleagues
Sarma Vrudhula: colleagues
Krzysztof Berezowski: colleagues