Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

ABSTRACT

The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in V_th can yield a temperature inversion effect causing a decreases of cell delay as temperature increases. This phenomenon, besides affecting timing analysis of a design, has important and unforeseeable consequences on power optimization techniques. In this paper, we focus on the impact of such effects on multi-V_t design; in particular, we show how traditional dual-V_t optimization may yield timing errors in circuits by ignoring temperature effects. Moreover, we present a temperature-aware dual-V_t optimization technique that reduces leakage power and can guarantee that the circuit is timing feasible at the boundary temperatures provided by the technology library. Our experiments show an average 27% leakage reduction with respect to a non temperature-aware design flow.

REFERENCES

• 1: K. Banerjee and A. Mehrotra. Global (interconnect) warming. IEEE Circuits and Devices Magazine, pages 16--32, 2001.
• 2: Andrea Calimera , Enrico Macii , Massimo Poncino , R. Iris Bahar, Temperature-insensitive synthesis using multi-vt libraries, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA [doi>10.1145/1366110.1366116]
• 3: Ali Dasdan , Ivan Hom, Handling inverted temperature dependence in static timing analysis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.306-324, April 2006 [doi>10.1145/1142155.1142158]
• 4: R. Kumar and V. Kursun. Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits. IEEE Trans. on Circuits and Systems, 53(10):1078--1082, Oct. 2006.
• 5: B. Lasbouygues, R. Wilson, N. Azemard, and P. Maurine. Temperature- and voltage-aware timing analysis. IEEE Transactions on CAD, 26(4):801--815, Apr. 2007.
• 6: T. Sakurai and A. R. Newton. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal on Solid-State Circuits, 25(2):584--594, Apr. 1990.
• 7: Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan, Temperature-Aware Computer Systems: Opportunities and Challenges, IEEE Micro, v.23 n.6, p.52-61, November 2003 [doi>10.1109/MM.2003.1261387]
• 8: Q. Wang and S. Vrudhula. Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. IEEE Trans. on CAD, 21(3):306--318, Mar. 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Design, Performance

Keywords:
logic synthesis, multi-V_t, temperature-aware