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Frequency planning for multi-core processors under thermal constraints
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International Symposium on Low Power Electronics and Design archive
Proceeding of the 13th international symposium on Low power electronics and design table of contents
Bangalore, India
POSTER SESSION: Poster session table of contents
Pages 213-216  
Year of Publication: 2008
ISBN:978-1-60558-109-5
Authors
Michael Kadin  Brown University, Providence, RI, USA
Sherief Reda  Brown University, Providence, RI, USA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 15,   Downloads (12 Months): 104,   Citation Count: 1
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ABSTRACT

The objectives of this paper are (1) to develop a frequency planning methodology that maximizes the total performance of multi-core processors and that limits their maximum temperature as specified by the design constraints; and (2) to establish the implications of technology scaling on the performance limits of multi-core processors. Given the intricate designs and workloads of multi or many-core processors, it is computationally exhaustive to develop models that accurately calculate the temperature and performance of a given processor under various operating conditions. To abstract the underlying design complexity, we propose the use of supervised machine learning techniques to develop versatile models that capture the thermal characterization of multi-core processors under various input conditions and workloads. We then use the developed models to create a framework where various design constraints and objectives are expressed and solved using combinatorial optimization techniques. Using established power modeling and thermal simulation tools, we show that it is possible to boost the performance of multi-core processors by up to 11.4% at no impact to the maximum temperature.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
"International Technology Roadmap for Semiconductors." {Online}. Available: http://public.itrs.net.
 
2
J. Boyd, "Native Quad Core Joins X86 Fray," in EETimes.com, 10/01/2007.
 
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W. Liao, L. He, and K. Lepak, "Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level," Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24(7), pp. 1042--1053, 2005.
 
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K. Skadron, S. Ghosh, S. Velusamy, K. Sankaranarayanan, and M. Stan, "HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design," Transactions on VLSI Systems, vol. 15(5), pp. 501--513, 2006.
 
12
S. Wilton and N. P. Jouppi, "CACTI: An Enhanced Cache Access and Cycle Time Model," IEEE Journal Solid-State Circuits, vol. 31(5), pp. 677--688, 1996.


Collaborative Colleagues:
Michael Kadin: colleagues
Sherief Reda: colleagues