| Frequency planning for multi-core processors under thermal constraints |
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International Symposium on Low Power Electronics and Design
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Proceeding of the 13th international symposium on Low power electronics and design
table of contents
Bangalore, India
POSTER SESSION: Poster session
table of contents
Pages 213-216
Year of Publication: 2008
ISBN:978-1-60558-109-5
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Downloads (6 Weeks): 15, Downloads (12 Months): 104, Citation Count: 1
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ABSTRACT
The objectives of this paper are (1) to develop a frequency planning methodology that maximizes the total performance of multi-core processors and that limits their maximum temperature as specified by the design constraints; and (2) to establish the implications of technology scaling on the performance limits of multi-core processors. Given the intricate designs and workloads of multi or many-core processors, it is computationally exhaustive to develop models that accurately calculate the temperature and performance of a given processor under various operating conditions. To abstract the underlying design complexity, we propose the use of supervised machine learning techniques to develop versatile models that capture the thermal characterization of multi-core processors under various input conditions and workloads. We then use the developed models to create a framework where various design constraints and objectives are expressed and solved using combinatorial optimization techniques. Using established power modeling and thermal simulation tools, we show that it is possible to boost the performance of multi-core processors by up to 11.4% at no impact to the maximum temperature.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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"International Technology Roadmap for Semiconductors." {Online}. Available: http://public.itrs.net.
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2
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J. Boyd, "Native Quad Core Joins X86 Fray," in EETimes.com, 10/01/2007.
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3
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4
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5
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6
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W. Liao, L. He, and K. Lepak, "Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level," Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24(7), pp. 1042--1053, 2005.
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7
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Grigorios Magklis , Greg Semeraro , David H. Albonesi , Steven G. Dropsho , Sandhya Dwarkadas , Michael L. Scott, Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor, IEEE Micro, v.23 n.6, p.62-68, November 2003
[doi> 10.1109/MM.2003.1261388]
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Srinivasan Murali , Almir Mutapcic , David Atienza , Rajesh Gupta , Stephen Boyd , Giovanni De Micheli, Temperature-aware processor frequency assignment for MPSoCs using convex optimization, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
[doi> 10.1145/1289816.1289845]
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K. Skadron, S. Ghosh, S. Velusamy, K. Sankaranarayanan, and M. Stan, "HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design," Transactions on VLSI Systems, vol. 15(5), pp. 501--513, 2006.
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12
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S. Wilton and N. P. Jouppi, "CACTI: An Enhanced Cache Access and Cycle Time Model," IEEE Journal Solid-State Circuits, vol. 31(5), pp. 677--688, 1996.
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