ACM Home Page
Please provide us with feedback. Feedback
Proactive temperature management in MPSoCs
Full text PdfPdf (481 KB)
Source
International Symposium on Low Power Electronics and Design archive
Proceeding of the 13th international symposium on Low power electronics and design table of contents
Bangalore, India
SESSION: Multi-core power optimization table of contents
Pages 165-170  
Year of Publication: 2008
ISBN:978-1-60558-109-5
Authors
Ayse Kivilcim Coskun  UC San Diego, La Jolla, CA, USA
Tajana Simunic Rosing  UC San Diego, La Jolla, CA, USA
Kenny C. Gross  Sun Microsystems, San Diego, CA, USA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): n/a,   Downloads (12 Months): n/a,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1393921.1393966
What is a DOI?

ABSTRACT

Preventing thermal hot spots and large temperature variations on the die is critical for addressing the challenges in system reliability, performance, cooling cost and leakage power. Reactive thermal management methods, which take action after temperature reaches a given threshold, maintain the temperature below a critical level at the cost of performance, and do not address the temperature variations. In this work, we propose a proactive thermal management approach, which estimates the future temperature using regression, and allocates workload on a multicore system to reduce and balance the temperature to avoid temperature induced problems. Our technique reduces the hot spots and temperature variations significantly in comparison to reactive strategies.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
A. H. Ajami, K. Banerjee, and M. Pedram. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Transactions on CAD, 24(6):849--861, June 2005.
 
2
3
 
4
5
6
 
7
K. Gross, K. Whisnant, and A. Urmanov. Electronic prognostics through continuous system telemetry. In MFPT, pages 53--62, April 2006.
 
8
 
9
 
10
Failure mechanisms and models for semiconductor devices, JEDEC publication JEP122C. http://www.jedec.org.
 
11
H. Kufluoglu and M. A. Alam. A computational model of NBTI and hot carrier injection time-exponents for MOSFET reliability. Journal of Computational Electronics, 3 (3):165--169, Oct. 2004.
12
 
13
A. Leon, L. Jinuk, K. Tam, W. Bryg, F. Schumacher, P. Kongetira, D. Weisner, and A. Strong. A power-efficient high-throughput 32-thread SPARC processor. ISSCC, 2006.
14
15
 
16
P. Rong and M. Pedram. Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system.
 
17
 
18
19
 
20
SLAMD Distributed Load Engine. www.slamd.com.
21
22
23

Collaborative Colleagues:
Ayse Kivilcim Coskun: colleagues
Tajana Simunic Rosing: colleagues
Kenny C. Gross: colleagues